IMX8MPCEC datasheet(80/111 Pages) NXP

80 / 111 page

i.MX 8M Plus Applications Processor Datasheet for Consumer Products, Rev. 0, 03/2021

NXP Semiconductors

Electrical characteristics

Figure 48. SAI Timing — Slave Modes

3.8.14 SPDIF timing parameters

The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When

encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.

Table 69, Figure 49, and Figure 50 show SPDIF timing parameters for the Sony/Philips Digital

Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for

SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.

S13

SAI_FS input setup before SAI_BCLK

—

S14

SAI_FA input hold after SAI_BCLK

—

S15

SAI_BCLK to SAI_TXD/SAI_FS output valid

—

S16

SAI_BCLK to SAI_TXD/SAI_FS output invalid

—

S17

SAI_RXD setup before SAI_BCLK

—

S18

SAI_RXD hold after SAI_BCLK

—

Table 69. SPDIF timing parameters

Parameter

Symbol

Timing Parameter Range

Unit

Min

Max

SPDIF_IN Skew: asynchronous inputs, no specs apply

—

0.7

SPDIF_OUT output (Load = 50 pf)

• Skew

• Transition rising

• Transition falling

—

1.5

24.2

31.3

Table 68. Slave mode SAI timing (25 MHz) (continued)

Num

Characteristic

Min

Max

Unit

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