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DA7217

Ultra-Low Power Stereo Codec

Datasheet

Revision 3.5

23-Feb-2022

CFR0011-120-00

41 of 169

9.3.3

Tone Generator

The tone generator contains two independent Sine Wave Generators (SWGs). Each SWG can

generate a sine wave at a frequency (FREQ) from approximately 1 Hz to 12 kHz according to the

programmed 16-bit value:

● FREQ[15:0] = 216 * fSWG/12000, for SR2 = (8, 12, 16, 24, 32, 48,96) kHz

● FREQ[15:0] = 216 * fSWG/11025, for SR2 = (11.025, 22.05, 44.1, 88.2) kHz

The DA7217 should not be programmed with frequency greater than the Nyquist frequency.

Nyquist frequency = SR2/2

For the first SWG, the FREQ value is stored in two 8-bit registers as freq1_u = FREQ[15:8] and

freq1_l = FREQ[7:0]. The second SWG frequency is programmed in the same way using freq2_u and

freq2_l. The output of the tone generator can come from either of the SWGs, or from a combination

of both of them as specified by swg_sel. In addition the tone generator can produce standard Dual

Tone Multi-Frequency (DTMF) tones using the two SWGs if dtmf_en = 1 and the required keypad

value is programmed in dtmf_reg as shown in Table 34.

Table 34: DTMF Tones Corresponding to dtmf_reg Value

The tone generator can produce 1, 2, 3, 4, 8, 16, or 32 beeps, or a continuous beep, as determined

by beep_cycles. Each beep has an on period from 10 ms to 2 s as programmed in beep_on_per and

an off period from 10 ms to 2 s as programmed in beep_off_per. The tone generator is started by

setting the start_stopn bit, and is halted by clearing this bit. If start_stopn is cleared, the tone

generator stops at the completion of the current beep cycle or at the next zero-cross if the number of

beeps is set to continuous (beep_cycles = 110 or = 111). The start_stopn bit is automatically cleared

once the programmed number of beep cycles has been completed.

The tone generator can also be used to produce an S-ramp by setting swg_sel to 0x03. System

Controller

The system controller (SC) automates the sequencing of the multiple blocks required to set up one or

more particular audio paths. It is an optional feature, and operates by performing register writes with

optimal sequencing and timing, thus eliminating pops and clicks.

The inputs are controlled using SYSTEM_MODES_INPUT, and the outputs are controlled using

SYSTEM_MODES_OUTPUT. Writing to the mode_submit field of either of these registers will cause

the system controller (SC) to process both input and output paths.

When the SC is activated by asserting the mode_submit field, all of the register-writes that are

required by the selected sub systems are performed automatically. Each sub-system is brought up,

or down, in the correct order to avoid pops and clicks. In addition, within each sub system, the

component parts are brought up in the correct pop-free and click-free sequence.

SWG2 Freq (Hz)

SWG1 Frequency (Hz)

1209

1336

1477

1633

697

0x1

0x2

0x3

0xA

770

0x4

0x5

0x6

0xB

852

0x7

0x8

0x9

0xC

941

0xE (✴)

0x0

0xF (#)

0xD

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