DA7217 datasheet(5/170 Pages) RENESAS

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DA7217

Ultra-Low Power Stereo Codec

Datasheet

Revision 3.5

23-Feb-2022

CFR0011-120-00

5 of 169

9.4.2

Headphone Amplifiers ......................................................................................... 54

9.4.3

Charge Pump Control .......................................................................................... 57

9.4.3.1

Charge Pump Initial and Switching Current .................................... 58

9.4.4

Tracking the Demands on the Charge Pump Output .......................................... 58

9.4.4.1

cp_mchange = 00 (Manual Mode)................................................... 58

9.4.4.2

cp_mchange = 01 (Tracking the PGA Gain Setting) ....................... 58

9.4.4.3

cp_mchange = 10 (Tracking the DAC Signal Setting)..................... 58

9.4.4.4

cp_mchange = 11 (Tracking the Output Signal Magnitude) ............ 59

9.4.5

Specifying Clock Frequencies when Tracking the Charge Pump Output

Demand ............................................................................................................... 60

9.4.6

Other Charge Pump Controls .............................................................................. 60

9.4.7

True-Ground Supply Mode .................................................................................. 60

9.5

Phase Locked Loop ............................................................................................................ 60

9.5.1

PLL Bypass Mode................................................................................................ 60

9.5.2

Normal PLL Mode (DAI Master) .......................................................................... 61

9.5.3

Example Calculation of the Feedback Divider Setting: ....................................... 62

9.5.4

Sample Rate Matching PLL Mode (DAI Slave) ................................................... 62

9.5.5

MCLK Input .......................................................................................................... 63

9.5.5.1

MCLK Detection............................................................................... 63

9.5.6

Audio Reference Oscillator .................................................................................. 63

9.5.6.1

Oscillator Calibration........................................................................ 63

9.5.6.2

Procedure for Calibrating the Reference Oscillator ......................... 64

9.5.7

Internal System Clock.......................................................................................... 64

9.6

Reference Generation......................................................................................................... 64

9.6.1

Voltage References ............................................................................................. 64

9.6.2

Bias Currents ....................................................................................................... 64

9.6.3

Voltage Levels ..................................................................................................... 64

9.6.3.1

Digital Regulator .............................................................................. 64

9.6.3.2

Digital Input/Output Pins Voltage Level ........................................... 65

9.7

I2C Control Interface............................................................................................................ 65

9.8

Digital Audio Interface ......................................................................................................... 68

9.8.1

DAI Channels....................................................................................................... 69

9.8.2

DAI WCLK Tristate Mode .................................................................................... 70

9.9

Interrupt Control .................................................................................................................. 70

9.9.1

Level Detect Events............................................................................................. 70

9.10 System Settings .................................................................................................................. 71

9.10.1

Sample Rate ........................................................................................................ 71

9.10.2

Gain Ramp Rate .................................................................................................. 71

9.10.3

Program Counter Control..................................................................................... 71

9.10.4

Soft Reset ............................................................................................................ 71

10 Register Maps and Definitions................................................................................................... 72

11 Package Information ................................................................................................................. 156

12 External Components ............................................................................................................... 157

13 Ordering Information ................................................................................................................ 158

Appendix A Applications Information ........................................................................................... 159

A.1

Codec Initialization ............................................................................................................ 159

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