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DA7217 Arkusz danych(PDF) 65 Page - Renesas Technology Corp |
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DA7217 Arkusz danych(HTML) 65 Page - Renesas Technology Corp |
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65 / 170 page ![]() DA7217 Ultra-Low Power Stereo Codec Datasheet Revision 3.5 23-Feb-2022 CFR0011-120-00 65 of 169 © 2022 Renesas Electronics Table 49: Audio Sub-System Digital LDO Level ldo_level_select Setting LDO Level (V) 00 1.05 01 1.10 10 1.20 11 1.40 9.6.3.2 Digital Input/Output Pins Voltage Level The digital input/output (I/O) pins can be set to operate in either a high voltage (2.5 V to 3.6 V) or low voltage (1.5 V to 2.5 V) range using the io_voltage_level bit. This bit should be set to the relevant value based on the IO voltage level of the host. 9.7 I2C Control Interface The DA7217 is completely software-controlled from the host via register writes. The DA7217 provides an I2C compliant serial control interface to access these registers. Data is shifted into or out of the DA7217 under the control of the host processor, which also provides the serial clock. The I2C clock is supplied by the SCL line and the bi-directional I2C data is carried by the SDA line. The I2C interface is open-drain supporting multiple devices on a single line. The bus lines have to be pulled High by external pull-up resistors (1 kΩ to 20 kΩ range). The attached devices only drive the bus lines Low by connecting them to ground. This means that two devices cannot conflict if they drive the bus simultaneously. Table 50: Device 7-Bit I2C Slave Addresses Pin AD Device I2C Address High 1B Low 1A In standard/fast mode the highest frequency of the bus is 1 MHz. The exact frequency can be determined by the application and does not have any relation to the DA7217 internal clock signals. DA7217 will follow the host clock speed within the described limitations and does not initiate any clock arbitration or slow down. In high-speed mode the maximum frequency of the bus can be increased up to 3.4 MHz. This mode is supported if the SCL line is driven with a push-pull stage from the host and if the host enables an external 3 mA pull-up at the SDA pin to decrease the rise time of the data. In this mode the SDA line on DA7217 is able to sink up to 12 mA. In all other respects the high speed mode behaves as the standard/fast mode. Communication on the I2C bus always takes place between two devices, one acting as the master and the other as the slave. The DA7217 will only operate as a SLAVE in I2C communication. |
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