ADV7342 datasheet(48/88 Pages) AD

48 / 88 page

ADV7342/ADV7343

Rev. 0 | Page 48 of 88

FEATURES

OUTPUT OVERSAMPLING

The ADV7342/ADV7343 include two on-chip phase locked

loops (PLLs) that allow for oversampling of SD, ED, and HD

video data. Table 36 shows the various oversampling rates

supported in the ADV7342/ADV7343.

SD Only, ED Only, and HD Only Modes

PLL 1 is used in SD only, ED only, and HD only modes. PLL 2 is

unused in these modes. PLL 1 is disabled by default and can be

enabled using Subaddress 0x00, Bit 1 = 0.

SD and ED/HD Simultaneous Modes

Both PLL 1 and PLL 2 are used in simultaneous modes. The use

of two PLLs allows for independent oversampling of SD and

ED/HD video. PLL 1 is used to oversample SD video data, and

PLL 2 is used to oversample ED/HD video data. In simultaneous

modes, PLL 2 is always enabled. PLL 1 is disabled by default and

can be enabled using Subaddress 0x00, Bit 1 = 0.

ED/HD NONSTANDARD TIMING MODE

Subaddress 0x30, Bits[7:3] = 00001

For any ED/HD input data that does not conform to the

standards available in the ED/HD input mode table

(Subaddress 0x30, Bits[7:3]), the ED/HD nonstandard timing

mode can be used to interface to the ADV7342/ADV7343.

ED/HD nonstandard timing mode can be enabled by setting

Subaddress 0x30, Bits[7:3] to 00001.

A clock signal must be provided on the CLKIN_A pin.

P_HSYNC and P_VSYNC must be toggled by the user to

generate the appropriate horizontal and vertical synchronization

pulses on the analog output from the encoder. Figure 59 illustrates

the various output levels that can be generated .Table 37 lists the

transitions required to generate these output levels.

Embedded EAV/SAV timing codes are not supported in

ED/HD nonstandard timing mode.

The user must ensure that appropriate pixel data is applied to

the encoder where the blanking level is expected at the output.

Macrovision (ADV7342 only) and output oversampling are not

available in ED/HD nonstandard timing mode.

ACTIVE VIDEO

ANALOG

OUTPUT

a = TRI-LEVEL SYNCHRONIZATION PULSE LEVEL.

b = BLANKING LEVEL/ACTIVE VIDEO LEVEL.

c = SYNCHRONIZATION PULSE LEVEL.

BLANKING LEVEL

Figure 59. ED/HD Nonstandard Timing Mode Output Levels

Table 36. Output Oversampling Modes and Rates

Input Mode

Subaddress 0x01 [6:4]

PLL and Oversampling Control

Subaddress 0x00, Bit 1

Oversampling Mode and Rate

000

SD only

SD (2×)

000

SD only

SD (16×)

001/010

ED only

ED (1×)

001/010

ED only

ED (8×)

001/010

HD only

HD (1×)

001/010

HD only

HD (4×)

011/100

SD and ED

SD (2×) and ED (8×)

011/100

SD and ED

SD (16×) and ED (8×)

011/100

SD and HD

SD (2×) and HD (4×)

011/100

SD and HD

SD (16×) and HD (4×)

111

ED only (at 54 MHz)

ED only (at 54 MHz) (1×)

111

ED only (at 54 MHz)

ED only (at 54 MHz) (8×)

Table 37. ED/HD Nonstandard Timing Mode Synchronization Signal Generation

Output Level Transition1

P_HSYNC

P_VSYNC

→ c

→ 0

→ 0 or 02

→ a

→ 1

→ b

→ 1

→ b

→ 1

1 a = tri-level synchronization pulse level; b = blanking level/active video level; c = synchronization pulse level.

2 If P_VSYNC = 1, it should transition to 0. If P_VSYNC = 0, it should remain at 0. If tri-level synchronization pulse generation is not required, P_VSYNC should always be 0.

ADV7342 Arkusz danych(PDF) 48 Page - Analog Devices

ADV7342 Arkusz danych(HTML) 48 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

Arkusz danych Pobierz

Link URL