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ADV7342 Arkusz danych(PDF) 14 Page - Analog Devices

Numer części ADV7342
Szczegółowy opis  Multiformat Video Encoder Six, 11-Bit, 297 MHz DACs
PDF  88 Pages
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Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

ADV7342 Arkusz danych(HTML) 14 Page - Analog Devices

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ADV7342/ADV7343
Rev. 0 | Page 14 of 88
Y0
Y1
Y2
Y3
b
a
Cr2
Cb2
Cr0
Cb0
c
Y OUTPUT
P_HSYNC
P_VSYNC
P_BLANK
Y7 TO Y0
C7 TO C0
a AND b AS PER RELEVANT STANDARD.
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
Figure 14. ED-SDR, 16-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Y7 TO Y0
Cb0
Y0
Cr0
Y1
b
a
a = 32 CLOCK CYCLES FOR 525p
a = 24 CLOCK CYCLES FOR 625p
AS RECOMMENDED BY STANDARD
b(MIN) = 244 CLOCK CYCLES FOR 525p
b(MIN) = 264 CLOCK CYCLES FOR 625p
P_HSYNC
P_VSYNC
P_BLANK
c
Y OUTPUT
c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME
EQUAL TO THE PIPELINE DELAY.
Figure 15. ED-DDR, 8-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram



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