ADV7342 datasheet(77/88 Pages) AD

77 / 88 page

ADV7342/ADV7343

Rev. 0 | Page 77 of 88

622

623

624

625

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

FIELD

DISPLAY

309

310

311

312

313

314

315

316

317

318

319

334

335

336

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

DISPLAY

320

FIELD

HSYNC

Figure 105. SD Slave Mode 1, PAL

Mode 1—Master Option (Subaddress 0x8A = X X X X X 0 1 1)

In this mode, the ADV7342/ADV7343 can generate horizontal sync and odd/even field signals. When HSYNC is low, a transition of the

field input indicates a new frame, that is, vertical retrace. The ADV7342/ADV7343 automatically blank all normally blank lines as per

CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. HSYNC and FIELD are output on the

S_HSYNC and S_VSYNC pins, respectively.

FIELD

PIXEL

DATA

HSYNC

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 106. SD Timing Mode 1, Odd/Even Field Transitions (Master/Slave)

Mode 2— Slave Option (Subaddress 0x8A = X X X X X 1 0 0)

In this mode, the ADV7342/ADV7343 accept horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC

inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The

ADV7342/ADV7343 automatically blank all normally blank lines as per CCIR-624. HSYNC and VSYNC are input on the S_HSYNC and

S_VSYNC pins, respectively.

ADV7342 Arkusz danych(PDF) 77 Page - Analog Devices

ADV7342 Arkusz danych(HTML) 77 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

Arkusz danych Pobierz

Link URL