ADV7342 datasheet(10/88 Pages) AD

10 / 88 page

ADV7342/ADV7343

Rev. 0 | Page 10 of 88

TIMING DIAGRAMS

The following abbreviations are used in Figure 2 to Figure 13:

•

t9 = Clock high time

•

t10 = Clock low time

•

t11 = Data setup time

•

t12 = Data hold time

•

t13 = Control output access time

•

t14 = Control output hold time

In addition, refer to Table 31 for the ADV7342/ADV7343 input

configuration.

CLKIN_A

t10

CONTROL

OUTPUTS

S_HSYNC,

S_VSYNC

Cr2

Cb2

Cr0

Cb0

*SELECTED BY SUBADDRESS 0x01, BIT 7.

IN MASTER/SLAVE MODE

IN SLAVE MODE

S7 TO S0/

Y7 TO Y0*

CONTROL

INPUTS

t12

t11

t13

t14

Figure 2. SD Only, 8-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000)

IN MASTER/SLAVE MODE

IN SLAVE MODE

CLKIN_A

CONTROL

OUTPUTS

S_HSYNC,

S_VSYNC

*SELECTED BY SUBADDRESS 0x01, BIT 7.

S7 TO S0/

Y7 TO Y0*

Y7 TO Y0/

C7 TO C0*

CONTROL

INPUTS

t10

Cr2

Cb2

Cr0

Cb0

t12

t14

t11

t13

Figure 3. SD Only, 16-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000)

C7 TO C0

Y7 TO Y0

CONTROL

OUTPUTS

S7 TO S0

CLKIN_A

t10

S_HSYNC,

S_VSYNC

CONTROL

INPUTS

t11

t12

t14

t13

Figure 4. SD Only, 24-Bit, 4:4:4 RGB Pixel Input Mode (Input Mode 000)

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