ADV7342 datasheet(27/88 Pages) AD

27 / 88 page

ADV7342/ADV7343

Rev. 0 | Page 27 of 88

A microprocessor can read from or write to all registers of the

ADV7342/ADV7343 via the MPU port, except for registers that

are specified as read-only or write-only registers.

The subaddress register determines which register the next

read or write operation accesses. All communication through

the MPU port starts with an access to the subaddress register.

A read/write operation is then performed from/to the target

address, which increments to the next address until the

transaction is complete.

Table 14 to Table 28 describe the functionality of each register.

All registers can be read from as well as written to, unless

otherwise stated.

SUBADDRESS REGISTER (SR7 TO SR0)

The subaddress register is an 8-bit write-only register. After the

MPU port is accessed and a read/write operation is selected, the

subaddress is set up. The subaddress register determines to or

from which register the operation takes place.

Table 14. Register 0x00

SR7 to

Bit Number

Reset

SR0

Bit Description

Setting

Value

Sleep

mode off.

0x12

Sleep Mode. With this control enabled, the current consumption is

reduced to μA level. All DACs and the internal PLL circuit are

disabled. I2C registers can be read from and written to in sleep mode.

Sleep

mode on.

PLL on.

PLL and Oversampling Control. This control allows the internal PLL

circuit to be powered down and the oversampling to be switched off.

PLL off.

DAC 3 off.

DAC 3: Power on/off.

DAC 3 on.

DAC 2 off.

DAC 2: Power on/off.

DAC 2 on.

DAC 1 off.

DAC 1: Power on/off.

DAC 1 on.

DAC 6 off.

DAC 6: Power on/off.

DAC 6 on.

DAC 5 off.

DAC 5: Power on/off.

DAC 5 on.

DAC 4 off.

0x00

Power

Mode

DAC 4: Power on/off.

DAC 4 on.

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