PIC12F683 datasheet(30/148 Pages) MICROCHIP

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PIC12F683

DS41211B-page 28

Preliminary

 2004 Microchip Technology Inc.

3.7.2

RESET OR WAKE-UP FROM SLEEP

The FSCM is designed to detect oscillator failure at any

point after the device has exited a Reset or Sleep con-

dition and the Oscillator Start-up Timer (OST) has

expired. If the external clock is EC or RC mode,

monitoring will begin immediately following these

events.

For LP, XT or HS mode the external oscillator may

require a start-up time considerably longer than the

FSCM sample clock time or a false clock failure may be

detected (see Figure 3-9). To prevent this, the internal

oscillator is automatically configured as the system

clock and functions until the external clock is stable (the

OST has timed out). This is identical to Two-Speed

Start-up mode. Once the external oscillator is stable,

the LFINTOSC returns to its role as the FSCM source.

OSCCON – OSCILLATOR CONTROL REGISTER (ADDRESS: 8Fh)

Note:

Due to the wide range of oscillator start-up

times, the Fail-Safe circuit is not active

during oscillator start-up (i.e., after exiting

Reset or Sleep). After an appropriate

amount of time, the user should check the

OSTS bit (OSCCON<3>) to verify the

oscillator

start-up

and

system

clock

switchover has successfully completed.

U-0

R/W-1

R/W-0

R-1

R-0

R/W-0

—

IRCF2

IRCF1

IRCF0

OSTS(1)

HTS

LTS

SCS

bit 7

bit 0

bit 7

Unimplemented: Read as ‘0’

bit 6-4

IRCF<2:0>: Internal Oscillator Frequency Select bits

000

= 31 kHz

001

= 125 kHz

010

= 250 kHz

011

= 500 kHz

100

= 1 MHz

101

= 2 MHz

110

= 4 MHz

111

= 8 MHz

bit 3

OSTS: Oscillator Start-up Time-out Status bit

= Device is running from the external system clock defined by FOSC<2:0>

= Device is running from the internal system clock (HFINTOSC or LFINTOSC)

bit 2

HTS: HFINTOSC (High Frequency – 8 MHz to 125 kHz) Status bit

=HFINTOSC is stable

= HFINTOSC is not stable

bit 1

LTS: LFINTOSC (Low Frequency – 31 kHz) Stable bit

= LFINTOSC is stable

= LFINTOSC is not stable

bit 0

SCS: System Clock Select bit

= Internal oscillator is used for system clock

= Clock source defined by FOSC<2:0>

Note 1:

Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the oscillator

mode or Fail-Safe mode is enabled.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

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