PIC12F683 datasheet(94/148 Pages) MICROCHIP

94 / 148 page

PIC12F683

DS41211B-page 92

Preliminary

 2004 Microchip Technology Inc.

FIGURE 12-10:

WAKE-UP FROM SLEEP THROUGH INTERRUPT

12.8

Code Protection

the

code

protection

bit(s)

have

not

been

programmed, the on-chip program memory can be

read out using ICSP for verification purposes.

12.9

ID Locations

Four memory locations (2000h-2003h) are designated

as ID locations where the user can store checksum or

other code identification numbers. These locations are

not accessible during normal execution but are readable

and writable during Program/Verify mode. Only the

Least Significant 7 bits of the ID locations are used.

12.10 In-Circuit Serial Programming

The PIC12F683 microcontrollers can be serially

programmed while in the end application circuit. This is

simply done with two lines for clock and data and three

other lines for:

•Power

•Ground

• Programming Voltage

This allows customers to manufacture boards with

unprogrammed devices and then program the micro-

controller just before shipping the product. This also

allows the most recent firmware or a custom firmware

to be programmed.

The device is placed into a Program/Verify mode by

holding the GP0 and GP1 pins low, while raising the

MCLR (VPP) pin from VIL to VIHH. See the “PIC12F6XX/

16F6XX

Memory

Programming

Specification”

(DS41204) for more information. GP0 becomes the

programming data and GP1 becomes the program-

ming clock. Both GP0 and GP1 are Schmitt Trigger

inputs in this mode.

After Reset, to place the device into Program/Verify

mode, the Program Counter (PC) is at location 00h. A

6-bit command is then supplied to the device.

Depending on the command, 14 bits of program data

are then supplied to or from the device, depending on

whether the command was a load or a read. For

complete details of serial programming, please refer to

the

“PIC12F6XX/16F6XX

Memory

Programming

Specification” (DS41204).

A typical In-Circuit Serial Programming connection is

shown in Figure 12-11.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

INTF flag

(INTCON<1>)

GIE bit

(INTCON<7>)

Instruction Flow

Instruction

Fetched

Instruction

Executed

PC + 1

PC + 2

Inst(PC) = Sleep

Inst(PC – 1)

Inst(PC + 1)

Sleep

Processor in

Sleep

Interrupt Latency(3)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Dummy Cycle

PC + 2

0004h

0005h

Dummy Cycle

TOST(2)

PC + 2

Note

XT, HS or LP Oscillator mode assumed.

TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC and RCIO Oscillator modes.

GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.

CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.

Note:

The entire data EEPROM and Flash

program memory will be erased when the

code protection is turned off. See the

PIC12F6XX/16F6XX Memory Program-

ming Specification (DS41204) for more

information.

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