PIC12F683 datasheet(35/148 Pages) MICROCHIP

35 / 148 page

 2004 Microchip Technology Inc.

Preliminary

DS41211B-page 33

PIC12F683

4.2.2

INTERRUPT-ON-CHANGE

Each of the GPIO pins is individually configurable as an

interrupt-on-change pin. Control bits IOCx enable or

disable the interrupt function for each pin. Refer to

Power-on Reset.

For enabled interrupt-on-change pins, the values are

compared with the old value latched on the last read of

GPIO. The ‘mismatch’ outputs of the last read are OR’d

together to set the GPIO Change Interrupt Flag bit

(GPIF) in the INTCON register.

This interrupt can wake the device from Sleep. The user,

in the Interrupt Service Routine, clears the interrupt by:

Any read or write of GPIO. This will end the

mismatch condition, then

Clear the flag bit GPIF.

A mismatch condition will continue to set flag bit GPIF.

Reading GPIO will end the mismatch condition and

allow flag bit GPIF to be cleared. The latch holding the

last read value is not affected by a MCLR nor BOD

Reset. After these resets, the GPIF flag will continue to

be set if a mismatch is present.

IOC – INTERRUPT-ON-CHANGE GPIO REGISTER (ADDRESS: 96h)

4.2.3

ULTRA LOW-POWER WAKE-UP

The Ultra Low-Power Wake-up (ULPWU) on GP0

allows a slow falling voltage to generate an interrupt-

on-change on GP0 without excess current consump-

tion. The mode is selected by setting the ULPWUE bit

(PCON<5>). This enables a small current sink which

can be used to discharge a capacitor on GP0.

To use this feature, the GP0 pin is configured to output

‘1’ to charge the capacitor, interrupt-on-change for GP0

is enabled and GP0 is configured as an input. The

ULPWUE bit is set to begin the discharge and a SLEEP

instruction is performed. When the voltage on GP0

drops below VIL, an interrupt will be generated which will

cause the device to wake-up. Depending on the state of

the GIE bit (INTCON<7>), the device will either jump to

the interrupt vector (0004h) or execute the next instruc-

tion when the interrupt event occurs. See Section 4.2.2

“Interrupt-on-change” and Section 12.4.3 “GPIO

Interrupt” for more information.

This feature provides a low-power technique for period-

ically waking up the device from Sleep. The time-out is

dependent on the discharge time of the RC circuit

on GP0. See Example 4-2 for initializing the Ultra

Low-Power Wake-up module.

The series resistor provides overcurrent protection for the

GP0 pin and can allow for software calibration of the time-

out (see Figure 4-1). A timer can be used to measure the

charge time and discharge time of the capacitor. The

charge time can then be adjusted to provide the desired

interrupt delay. This technique will compensate for the

affects of temperature, voltage and component accuracy.

The Ultra Low-Power Wake-up peripheral can also be

configured as a simple Programmable Low-Voltage

Detect or temperature sensor.

Note:

If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the GPIF

interrupt flag may not get set.

U-0

R/W-0

—

IOC5

IOC4

IOC3

IOC2

IOC1

IOC0

bit 7

bit 0

bit 7-6

Unimplemented: Read as ‘0’

bit 5-0

IOC<5:0>: Interrupt-on-change GPIO Control bit

= Interrupt-on-change enabled

= Interrupt-on-change disabled

Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be

recognized.

2: IOC<5:4> reads ‘1’ in XT, LP and HS modes.

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

Note:

For more information, refer to the Applica-

tion Note AN879, “Using the Microchip

Ultra

Low-Power

Wake-up

Module”

(DS00879).

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