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PIC12F683 Arkusz danych(PDF) 78 Page - Microchip Technology

Numer części PIC12F683
Szczegółowy opis  8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology
PDF  148 Pages
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Producent  MICROCHIP [Microchip Technology]
Strona internetowa  http://www.microchip.com
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PIC12F683 Arkusz danych(HTML) 78 Page - Microchip Technology

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PIC12F683
DS41211B-page 76
Preliminary
 2004 Microchip Technology Inc.
12.1
Configuration Bits
The configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’) to select various
device configurations as shown in Register 12-1.
These bits are mapped in program memory location
2007h.
REGISTER 12-1:
CONFIG – CONFIGURATION WORD (ADDRESS: 2007h)
Note:
Address
2007h is
beyond the user
program memory space. It belongs to the
special
configuration
memory
space
(2000h-3FFFh), which can be accessed
only
during
programming.
See
“PIC12F6XX/16F6XX Memory Program-
ming Specification” (DS41204) for more
information.
FCMEN
IESO
BODEN1 BODEN0
CPD
CP
MCLRE PWRTE
WDTE
FOSC2 FOSC1 FOSC0
bit 13
bit 0
bit 13-12
Unimplemented: Read as ‘1’
bit 11
FCMEN: Fail-Safe Clock Monitor Enabled bit
1
= Fail-Safe Clock Monitor is enabled
0
= Fail-Safe Clock Monitor is disabled
bit 10
IESO: Internal External Switchover bit
1
= Internal External Switchover mode is enabled
0
= Internal External Switchover mode is disabled
bit 9-8
BODEN<1:0>: Brown-out Detect Selection bits(1)
11
= BOD enabled
10
= BOD enabled during operation and disabled in Sleep
01
= BOD controlled by SBODEN bit (PCON<4>)
00
= BOD disabled
bit 7
CPD: Data Code Protection bit(2)
1
= Data memory code protection is disabled
0
= Data memory code protection is enabled
bit 6
CP: Code Protection bit(3)
1
= Program memory code protection is disabled
0
= Program memory code protection is enabled
bit 5
MCLRE: GP3/MCLR pin function select bit(4)
1
= GP3/MCLR pin function is MCLR
0
= GP3/MCLR pin function is digital input, MCLR internally tied to VDD
bit 4
PWRTE: Power-up Timer Enable bit
1
= PWRT disabled
0
= PWRT enabled
bit 3
WDTE: Watchdog Timer Enable bit
1
= WDT enabled
0
= WDT disabled and can be enabled by SWDTEN bit (WDTCON<0>)
bit 2-0
FOSC<2:0>: Oscillator Selection bits
111
= RC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN
110
= RCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN
101
= INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN
100
= INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN
011
= EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN
010
= HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN
001
= XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN
000
= LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN
Note 1:
Enabling Brown-out Detect does not automatically enable Power-up Timer.
2:
The entire data EEPROM will be erased when the code protection is turned off.
3:
The entire program memory will be erased when the code protection is turned off. When MCLR is asserted
in INTOSC or RC mode, the internal clock oscillator is disabled.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown



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