PIC12F615 datasheet(85/168 Pages) MICROCHIP

85 / 168 page

Preliminary

DS41302A-page 83

PIC12F609/615/12HV609/615

10.4

PWM (Enhanced Mode)

The Enhanced PWM Mode can generate a PWM signal

on up to four different output pins with up to 10-bits of

resolution. It can do this through four different PWM

output modes:

• Single PWM

• Half-Bridge PWM

To select an Enhanced PWM mode, the P1M bits of the

CCP1CON register must be set appropriately.

The PWM outputs are multiplexed with I/O pins and are

designated P1A and P1B. The polarity of the PWM pins

is configurable and is selected by setting the CCP1M

bits in the CCP1CON register appropriately.

Table 10-6 shows the pin assignments for each

Enhanced PWM mode.

Figure 10-5 shows an example of a simplified block

diagram of the Enhanced PWM module.

FIGURE 10-5:

EXAMPLE SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE

TABLE 10-6:

EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES

Note:

prevent

the

generation

incomplete waveform when the PWM is

first enabled, the ECCP module waits until

the start of a new PWM period before

generating a PWM signal.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(1)

Duty Cycle Registers

CCP1<1:0>

Clear Timer2,

toggle PWM pin and

latch duty cycle

Alternate pin function.

Note

The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler to create the 10-bit time base.

TRISIO2

CCP1/P1A

Output

Controller

P1M<1:0>

CCP1M<3:0>

PWM1CON

CCP1/P1A

P1B

TRISIO5

CCP1/P1A*

P1ASEL

(APFCON<0>)

TRISIO0

P1B

TRISIO4

P1B*

P1BSEL

(APFCON<1>)

Note 1: The TRIS register value for each PWM output must be configured appropriately.

2: Clearing the CCP1CON register will relinquish ECCP control of all PWM output pins.

3: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.

ECCP Mode

P1M<1:0>

CCP1/P1A

P1B

Single

Yes(1)

Half-Bridge

Yes

Note 1:

Pulse Steering enables outputs in Single mode.

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