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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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PIC12F615 Arkusz danych(PDF) 14 Page - Microchip Technology |
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PIC12F615 Arkusz danych(HTML) 14 Page - Microchip Technology |
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14 / 168 page  PIC12F609/615/12HV609/615 DS41302A-page 12 Preliminary © 2006 Microchip Technology Inc. TABLE 2-2: PIC12F615/HV615 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0 Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Page Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 22, 101 01h TMR0 Timer0 Module’s Register xxxx xxxx 41, 101 02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 22, 101 03h STATUS IRP(1) RP1(1) RP0 TO PD ZDC C 0001 1xxx 15, 101 04h FSR Indirect Data Memory Address Pointer xxxx xxxx 22, 101 05h GPIO — — GP5 GP4 GP3 GP2 GP1 GP0 --x0 x000 31, 101 06h — Unimplemented — — 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 22, 101 0Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 0000 17, 101 0Ch PIR1 — ADIF CCP1IF —CMIF — TMR2IF TMR1IF -00- 0-00 19, 101 0Dh — Unimplemented — — 0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 45, 101 0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx 45, 101 10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 49, 101 11h TMR2 Timer2 Module Register 0000 0000 51, 101 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 52, 101 13h CCPR1L Capture/Compare/PWM Register 1 Low Byte XXXX XXXX 76, 101 14h CCPR1H Capture/Compare/PWM Register 1 High Byte XXXX XXXX 76, 101 15h CCP1CON P1M — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0-00 0000 75, 101 16h PWM1CON PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 0000 0000 91, 101 17h ECCPAS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 0000 0000 88, 101 18h — Unimplemented — — 19h VRCON CMVREN — VRR FVREN VR3 VR2 VR1 VR0 0-00 0000 62, 101 1Ah CMCON0 CMON COUT CMOE CMPOL —CMR —CMCH 0000 -0-0 58, 101 1Bh — — — — — 1Ch CMCON1 — — — T1ACS CMHYS — T1GSS CMSYNC ---0 0-10 59, 101 1Dh — Unimplemented — — 1Eh ADRESH Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 71, 101 1Fh ADCON0 ADFM VCFG — CHS2 CHS1 CHS0 GO/DONE ADON 00-0 0000 70, 101 Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: IRP and RP1 bits are reserved, always maintain these bits clear. |
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