T48C862-R8 datasheet(71/107 Pages) ATMEL

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T48C862-R8

4590B–4BMCU–02/03

bit controls the direction of the data port (BP43 or MCL_SD). Once started, the 8 data

bits are, depending on the selected direction, either clocked into or out of the shift regis-

ter. During the 9th clock period, the port direction is automatically switched over so that

the corresponding acknowledge bit can be shifted out or read in. In transmit mode, the

acknowledge bit received from the device is captured in the SSI Status Register (TACK)

where it can be read by the controller. In receive mode, the state of the acknowledge bit

to be returned to the device is predetermined by the SSI Status Register (RACK).

Changing the directional mode (TX/RX) should not be performed during the transfer of

an MCL telegram. One should wait until the end of the telegram which can be detected

using the SSI interrupt (IFN =1) or by interrogating the ACT status.

Once started, a 9-bit telegram will always run to completion and will not be prematurely

terminated by the SIR bit. So, if the SIR-bit is set to ‘1’ in telegram, the SSI will complete

the current transfer and terminate the dialog with an MCL stop condition.

Figure 67. Example of MCL Transmit Dialog

7 6 54 32 1

7 65432 10 A

msb

lsb

tx data 1

tx data 2

msb

lsb

Write STB

(tx data 1)

SRDY

ACT

Interrupt

(IFN = 0)

Interrupt

(IFN = 1)

Write STB

(tx data 2)

SIR

SDD

Start

Stop

T48C862-R8 Arkusz danych(PDF) 71 Page - ATMEL Corporation