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V58C2128 Arkusz danych(PDF) 23 Page - Mosel Vitelic, Corp |
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V58C2128 Arkusz danych(HTML) 23 Page - Mosel Vitelic, Corp |
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23 / 59 page ![]() 23 MOSEL VITELIC V58C2128(804/404/164)S V58C2128(804/404/164)S Rev. 1.6 March 2002 Write Interrupted by a Read A Burst Write can be interrupted by a Read command to any bank. If a burst write operation is interrupted prior to the end of the burst operation, then the last two pieces of input data prior to the Read command must be masked off with the data mask (DM) input pin to prevent invalid data from being written into the memory array. Any data that is present on the DQ pins coincident with or following the Read command will be masked off by the Read command and will not be written to the array. The memory controller must give up control of both the DQ bus and the DQS bus at least one clock cycle before the read data appears on the outputs in order to avoid contention. In order to avoid data contention within the device, a delay is required (t CDLR) from the last valid data input before a Read command can be issued to the device. It is illegal to interrupt a Write with autoprecharge command with a Read command. Write Interrupted by a Read Command Timing Auto Refresh The Auto Refresh command is issued by having CS, RAS, and CAS held low with CKE and WE high at the rising edge of the clock. All banks must be precharged and idle for a t RP(min) before the Auto Refresh com- mand is applied. No control of the address pins is required once this cycle has started because of the internal address counter. When the Auto Refresh cycle has completed, all banks will be in the idle state. A delay be- tween the Auto Refresh command and the next Activate command or subsequent Auto Refresh command must be greater than or equal to the t RFC(min). Commands may not be issued to the device once an Auto Refresh cycle has begun. CS input must remain high during the refresh period or NOP commands must be registered on each rising edge of the CK input until the refresh period is satisfied. Auto Refresh Timing (CAS Latency = 2; Burst Length = 8) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 Write NOP Read NOP NOP NOP NOP NOP NOP NOP NOP CK, CK Command DQS T12 DM D2 D3 D4 D5 D0 D2 D3 D4 D5 D6 D1 D7 DQ Data is masked by Read command Data is masked by DM input DQS input ignored D0 D1 tWTR T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 NOP NOP NOP CK, CK Command CKE T11 Auto Ref ANY High Pre All tRFC tRP |
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