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V58C2128 Arkusz danych(PDF) 3 Page - Mosel Vitelic, Corp |
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V58C2128 Arkusz danych(HTML) 3 Page - Mosel Vitelic, Corp |
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3 / 59 page ![]() MOSEL VITELIC V58C2128(804/404/164)S 3 V58C2128(804/404/164)S Rev. 1.6 March 2002 Block Diagram Row decoder Memory array Bank 0 4096 x 1024 x 8 Row decoder Memory array Bank 1 Row decoder Memory array Bank 2 Row decoder Memory array Bank 3 Input buffer Output buffer DQ0-DQ3 Column address counter Column address buffer Row address buffer Refresh Counter A0 - A11, BA0, BA1 A0 - A9, A11, AP, BA0, BA1 Control logic & timing generator Row Addresses Column Addresses DLL Strobe Gen. Data Strobe CK, CK DQS 4096 x 1024 x 8 4096 x 1024 x 8 4096 x 1024 x 8 32M x 4 V 58 C 2 128(80/40/16) 4 S X T XX DDRSDRAM CMOS 2.5V 128Mb, 4K Refresh 4 Banks COMPONENT REV LEVEL COMPONENT PACKAGE, T = TSOP SSTL SPEED 6 (166MHZ@CL2.5) MOSEL VITELIC MANUFACTURED 7 (143MHZ@CL2.5)) 75(133MHZ@CL2.5) x8, x4, x16 8 (125MHZ@CL2.5) |
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