AT89LP428 datasheet(66/149 Pages) ATMEL

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3654A–MICRO–8/09

AT89LP428/828

Each CCA channel has an associated external capture input pin: CCA (P2.0), CCB (P2.1), CCC

(P2.2) and CCD (P2.3). External capture events are always edge-triggered and can be selected

to occur at a negative edge, positive edge, or both (toggle). Capture inputs are sampled every

clock cycle and a new value must be held for at least 2 clock cycles to be correctly sampled by

the device. The maximum achievable capture rate will be determined by how fast the software

can retrieve the captured data. There is no protection against capture events overrunning the

data register.

Capture events may also be triggered internally by the overflows of Timer 0 or Timer 1, or by an

event from the dual analog comparators. Any comparator event which can generate a compara-

tor interrupt may also be used as a capture event. However, Timer 2 should not be selected as

the comparator clock source when using the comparator as the capture trigger.

13.2.1

Timer 2 Operation for Capture Mode

Capture channels are intended to work with Timer 2 in capture mode CP/RL2 =1. Captures can

still occur when Timer 2 operates in other modes; however, the full 16-bit count range may not

be available. The TF2 flag can be used to determine if the timer overflowed before the capture

occurred. If the timer is operating in dual-slope mode (CP/RL2 =0, T2CM

1-0 =1xB), the count

direction (Up = 0 and Down = 1) at the time of the event will be captured into the channel’s

CDIRx bit in CCCx. CTCx must be cleared to 0 for all channels if Timer 2 is operating in Baud

Rate mode or errors may occur in the serial communication.

13.3

Output Compare Mode

The Compare/Capture Array provides a variety of compare modes suitable for event timing or

waveform generation. The CCA channels are configured for compare mode by setting the CCMx

bit in the associated CCCx register to 1. A compare event occurs when the 16-bit contents of a

channel’s data register match the contents of Timer 2 (TH2 and TL2). The compare event also

sets the channel’s interrupt flag CCFx in T2CCF and may optionally clear Timer 2 to 0000H if the

CTCx bit in CCCx is set. A diagram of a CCA channel in compare mode is shown in Figure 13-3.

Figure 13-3. CCA Compare Mode Diagram

TL2

TH2

CCxL

CCxH

CCCx

Interrupt

CCx (P2.x)

T2CCC

T2CCL

Shadow

00H

CTCx

CCFx

CIENx

CxM2-0

T2CCH

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