AT89LP428 datasheet(72/149 Pages) ATMEL

72 / 149 page

3654A–MICRO–8/09

AT89LP428/828

Figure 13-11. Phase Correct Symmetrical (Center-Aligned) PWM

13.4.3

Multi-Phasic PWM

The PWM channels may be configured to provide multi-phasic alternating outputs by the PHS

2-0

bits in T2MOD. The AT89LP428/828 provides 1 out of 2, 1 out of 3, 1 out of 4 and 2 out of 4

phase modes (see Table 13-6). In Multi-phasic mode, the PWM outputs on CCA, CCB, CCC and

CCD are connected to a one-hot shift register that selectively enables and disables the outputs

(see Figure 13-12). Compare points on disabled channels are blocked from toggling the output

as if the compare value was set equal to TOP. The PHSD bit in T2MOD controls the direction of

the shift register. Example waveforms are shown in Figure 13-13 on page 73. In order to use

multi-phasic PWM, the associated channels must be configured for PWM operation. Non-PWM

channels are not affected by multi-phasic operation. However, their locations in the shift register

are maintained such that some periods in the PWM outputs may not have any pulses as shown

in Figure 13-14.

The PHS

2-0 bits may only be modified when the timer is not operational (TR2 = 0). Updates to

PHSD are allowed at any time. Note that channels C and D in 1:2 phase mode and channel D in

1:3 phase mode operate normally.

{RCAP2H,RCA2L}

CP/RL2 = 0, T2CM1-0 = 11B, DCEN = 0

Inverted

{CCxH,CCxL}

Non-Inverted

CCx

Duty Cycle Updated

Table 13-6.

Summary of Multi-Phasic Modes

PHS2-0

Mode

Behavior

PHSD = 0

PHSD = 1

000

Off

Normal Operation (all channels active at all times)

001

1:2

010

1:3

011

1:4

100

2:4

ABAB

→→→

BABA

→→→

CABC

→→ →→→

CBACBA

→→→ → →

ABCDABCD

→→ → →→→ →

DCBADCBA

→ →→→ → → →

ABA

→→→

CDC

→→ →

BAB

→→→

DCD

→→ →

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