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AT89LP428 Arkusz danych(PDF) 56 Page - ATMEL Corporation |
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AT89LP428 Arkusz danych(HTML) 56 Page - ATMEL Corporation |
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56 / 149 page ![]() 56 3654A–MICRO–8/09 AT89LP428/828 12.3.1 Up Counter Figure 12-2 shows Timer 2 automatically counting up when DCEN = 0 and T2CM 1-0 = 00B. In this mode Timer 2 counts up to MAX and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with BOTTOM, the 16-bit value in RCAP2H and RCAP2L. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 tran- sition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt. The Timer 2 overflow rate for this mode is given in the following equation: Timer 2 may also be configured to count from MIN to TOP instead of BOTTOM to MAX by set- ting T2CM 1-0 = 01B. In this mode Timer 2 counts up to TOP, the 16-bit value in RCAP2H and RCAP2L and then overflows. The overflow sets TF2 and causes the timer registers to be reloaded with MIN. If EXEN2 = 1, a 1-to-0 transition on T2EX will clear the timer and set EXF2. The Timer 2 overflow rate for this mode is given in the following equation: Timer 2 Count Mode 1 is provided to support variable precision asymmetrical PWM in the CCA. The value of TOP stored in RCAP2H and RCAP2L is double-buffered such that a new TOP value takes affect only after an overflow. The behavior of Count Mode 0 versus Count Mode 1 is shown in Figure 12-3. Figure 12-2. Timer 2 Diagram: Auto-reload Mode (DCEN = 0) Auto-Reload Mode: DCEN = 0, T2CM = 00B Time-out Period 65536 RCAP2H RCAP2L {, } – Oscillator Frequency ------------------------------------------------------------------------------- TPS 1 + () × = Auto-Reload Mode: DCEN = 0, T2CM = 01B Time-out Period RCAP2H RCAP2L {, } 1 + Oscillator Frequency ------------------------------------------------------------------ TPS 1 + () × = ÷TPS TL2 TH2 Reload Transition Detector Timer 2 Interrupt Overflow |
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