TMS320VC33 datasheet(46/58 Pages) TI

46 / 58 page

TMS320VC33

DIGITAL SIGNAL PROCESSOR

SPRS087E -- FEBRUARY 1999 -- REVISED JANUARY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251--1443

data-rate timing modes

Unless otherwise indicated, the data-rate timings shown in Figure 31 and Figure 32 are valid for all serial-port

modes, including handshake. For a functional description of serial-port operation, see the TMS320C3x User’s

Guide (literature number SPRU031).

tsu(FSX--CLKX)

td(CLKX--FSX)

FSX(EXT)

FSX(INT)

FSR

CLKX/R

Bit 0

Bit n-1

Bit n-2

Bit n-1

Bit n-2

td(H1H-SCK)

tc(SCK)

tw(SCK)

tr(SCK)

tf(SCK)

td(CLKX--DX)

tsu(DR--CLKRL)

th(CLKRL--DR)

td(CLKX--FSX)

tsu(FSR--CLKRL)

th(SCKL--FS)

td(CLKX--DX)V

tdis(CLKX--DXZ)

NOTES: A. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = 0.

B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.

Figure 31. Fixed Data-Rate Mode Timing

CLKX/R

FSX(INT)

FSX(EXT)

FSR

Bit 0

Bit n-2

Bit n-3

Bit n-2

Bit n-3

Bit n-1

td(CLKX--FSX)

td(FSX--DX)V

tsu(FSX--CLKX)

tsu(DR--CLKRL)

td(CLKX--DX)

th(CLKRL-DR)

th(SCKL-FS)

tsu(FSR-CLKRL)

td(CLKX-DX)V

tdis(CLKX-DXZ)

NOTES: A. Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0.

B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.

C. The timings that are not specified expressly for the variable data-rate mode are the same as those that are specified for the fixed

data-rate mode.

Figure 32. Variable Data-Rate Mode Timing

TMS320VC33 Arkusz danych(PDF) 46 Page - Texas Instruments

TMS320VC33 Arkusz danych(HTML) 46 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

Arkusz danych Pobierz

Link URL