TMS320VC33 datasheet(16/58 Pages) TI

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TMS320VC33

DIGITAL SIGNAL PROCESSOR

SPRS087E -- FEBRUARY 1999 -- REVISED JANUARY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251--1443

PAGE0 -- PAGE3 select lines

To facilitate simpler and higher speed connection to external devices, the TMS320VC33 includes four

predecoded select pins that have the same timings as STRB. These pins are decoded from A22, A23, and STRB

and are active only during external accesses over the ranges shown in Table 3. All external bus accesses are

controlled by a single bus control register.

Table 3. PAGE0 -- PAGE3 Ranges

START

END

PAGE0

0x000000

0x3FFFFF

PAGE1

0x400000

0x7FFFFF

PAGE2

0x800000

0xBFFFFF

PAGE3

0xC00000

0xFFFFFF

using external logic with the READY pin

The key to designing external wait-state logic is the internal bus control register and associated internal logic

that logically combines the external READY pin with the much faster on-chip bus control logic. This essentially

allows slow external logic to interact with the bus while easily meeting the READY input timings. It is also relevant

to mention that the combined ready signals are sampled on the rising edge of the internal H1 clock. Please refer

to Figure 8 for the following examples.

example 1

A simple 0 or WTCNT wait-state decoder can be created by simply tying an address line back to the READY

pin and selecting the AND option. When the tied back address is low, the bus runs with 0 wait states. When the

tied back address is high, the bus will be controlled by the internal wait-state counter.

By enabling the bank compare logic, proper operation is further ensured by inserting a null cycle before a read

on the next bank is performed (writes are not pre-extended). This extra time can also be used by external logic

to affect the feedback path.

example 2

An N--WTCNT minimum wait-state decoder can also be created by tying back an address line to READY and

logically ORing it with the internal bank compare and wait count signals. When the address pin is low, bus timing

is determined by the internal WTCNT and BNKCMP settings. When the address line is high, the bus can run

no faster than the WTCNT counter and is extended as long as READY is held high.

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