TMS320VC33 datasheet(15/58 Pages) TI

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TMS320VC33

DIGITAL SIGNAL PROCESSOR

SPRS087E -- FEBRUARY 1999 -- REVISED JANUARY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251--1443

power sequencing considerations

Though an internal ESD and CMOS latchup protection diode exists between CVDD and DVDD, it should not be

considered a current-carrying device on power up. An external Schottky diode should be used to prevent CVDD

from exceeding DVDD by more than 0.7 V. The effect of this diode during power up is that if CVDD is powered

up first, DVDD follows by one diode drop even when the DVDD supply is not active.

Typical systems using LDOs of the same family type for both DVDD and CVDD will track each other during power

up. In most cases, this is acceptable; but if a high-impedance pin state is required on power up, the SHZ pin

can be used to asynchronously disable all outputs. RESET should not be used in this case since some signals

require an active clock for RESET to have an effect and the clock may not yet be active. The internal core logic

becomes functional at approximately 0.8 V while the external pin IO becomes active at about 1.5 V.

EDGEMODE

When EDGEMODE = 1, a sampled digital delay line is decoded to generate a pulse on the falling edge of the

interrupt pin. To ensure interrupt recognition, input signal logic-high and logic-low states must be held longer

than the synchronizer delay of one CPU clock cycle. Holding these inputs to no less than two cycles in both the

logic-low and logic-high states is sufficient.

When EDGEMODE = 0, a logic-low interrupt pin continually sets the corresponding interrupt flag. The CPU or

DMA can clear this flag within two cycles of it being set. This is the maximum interrupt width that can be applied

if only one interrupt is to be recognized. The CPU can manually clear IF bits within an interrupt service routine

(ISR), effectively lengthening the maximum ISR width.

After reset, EDGEMODE is temporarily disabled, allowing logic-low INT pins to be detected for bootload

operation.

INT

IF Bit

CPU_RESET

CPU_SET

Delay

RESET

EDGEMODE

Figure 7. EDGEMODE and Interrupt Flag CIrcuit

reset operation

When RESET is applied, the CPU attempts to safely exit any pending read or write operations that may be in

progress. This can take as much as 10 CPU cycles, after which, the address, data, and control pins will be in

an inactive or high-impedance state.

When both RESET and SHZ are applied, the device immediately enters the reset state with the pins held in

high-impedance mode. SHZ should then be disabled at least 10 CPU cycles before RESET is set high. SHZ

can be used during power-up sequencing to prevent undefined address, data, and control pins, avoiding system

conflicts.

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