ADV7341_15 datasheet(37/108 Pages) AD

37 / 108 page

Data Sheet

ADV7340/ADV7341

Rev. C | Page 37 of 108

Table 23. Register 0x34 to Register 0x35

SR7 to

Bit Number

Reset

SR0

Bit Description

Value

0x34

ED/HD Mode

ED/HD timing reset

Internal ED/HD timing counters enabled

0x48

Resets the internal ED/HD timing counters

ED/HD HSYNC control1

HSYNC output control (refer to

Table 56)

ED/HD VSYNC control1

VSYNC output control (refer to

Table 57)

ED/HD blank polarity

P_BLANK active high

P_BLANK active low

ED Macrovision® enable

Macrovision disabled

Macrovision enabled

Reserved

0 must be written to this bit

ED/HD VSYNC/field input

0 = field input

1 = VSYNC input

Horizontal/vertical counters2

Update field/line counter

Field/line counter free running

0x35

ED/HD Mode

Reserved

0x00

ED/HD RGB input enable

Disabled.

Enabled

ED/HD sync on PrPb

Disabled

Enabled

ED/HD color DAC swap

DAC 2 = Pb, DAC 3 = Pr

DAC 2 = Pr, DAC 3 = Pb

ED/HD gamma correction

curve select

Gamma Correction Curve A

Gamma Correction Curve B

ED/HD gamma correction

enable

Disabled

Enabled

ED/HD adaptive filter mode

Mode A

Mode B

ED/HD adaptive filter enable

Disabled.

Enabled

Used in conjunction with ED/HD sync output enable in Subaddress 0x02, Bit 7 = 1.

When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the

horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.

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