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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ADV7341 Arkusz danych(PDF) 13 Page - Analog Devices |
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ADV7341 Arkusz danych(HTML) 13 Page - Analog Devices |
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13 / 108 page  Data Sheet ADV7340/ADV7341 Rev. C | Page 13 of 108 TIMING DIAGRAMS The following abbreviations are used in Figure 2 to Figure 13: • t9 = clock high time • t10 = clock low time • t11 = data setup time • t12 = data hold time • t13 = control output access time • t14 = control output hold time In addition, refer to Table 36 for the ADV7340/ADV7341 input configuration. Figure 2. SD Only, 8-/10-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000) Figure 3. SD Only, 16-/20-Bit, 4:2:2 YCrCb Pixel Input Mode (Input Mode 000) t9 CLKIN_A t10 CONTROL OUTPUTS S_HSYNC, S_VSYNC Cr2 Cb2 Cr0 Cb0 *SELECTED BY SUBADDRESS 0x01, BIT 7. IN MASTER/SLAVE MODE IN SLAVE MODE Y0 Y1 Y2 S9 TO S0/ Y9 TO Y0* CONTROL INPUTS t12 t11 t13 t14 IN MASTER/SLAVE MODE IN SLAVE MODE CLKIN_A CONTROL OUTPUTS S_HSYNC, S_VSYNC *SELECTED BY SUBADDRESS 0x01, BIT 7. S9 TO S0/ Y9 TO Y0* Y9 TO Y0/ C9 TO C0* CONTROL INPUTS t9 t10 Cr2 Cb2 Cr0 Cb0 Y0 Y1 Y2 Y3 t12 t14 t11 t13 |
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