ADV7341_15 datasheet(87/108 Pages) AD

87 / 108 page

Data Sheet

ADV7340/ADV7341

Rev. C | Page 87 of 108

Figure 107. SD Slave Mode 2, PAL

Mode 2—Master Option (Subaddress 0x8A = X X X X X 1 0 1)

In this mode, the ADV7340/ADV7341 can generate horizontal and vertical sync signals. A coincident low transition of both HSYNC and

VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The

ADV7340/ADV7341 automatically blank all normally blank lines as required by the CCIR-624 standard. HSYNC and VSYNC are output

on the S_HSYNC and S_VSYNC pins, respectively.

Figure 108. SD Timing Mode 2, Even-to-Odd Field Transition (Master/Slave)

Figure 109. SD Timing Mode 2 Odd-to-Even Field Transition (Master/Slave)

622

623

624

625

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

DISPLAY

309

310

311

312

313

314

315

316

317

318

319

334

335

336

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

DISPLAY

320

HSYNC

VSYNC

HSYNC

VSYNC

PIXEL

DATA

HSYNC

VSYNC

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

PIXEL

DATA

HSYNC

VSYNC

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

PAL = 864 × CLOCK/2

NTSC = 858 × CLOCK/2

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