DATA SHEET • SKY73208-11 MIXER WITH PLL AND VCO

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201317F • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • November 5, 2015

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Table 2. SPI Timing Requirements

Timing

Description

Minimum Time

(ns)

Clock period

25

Clock high time

10

Data setup to clock rise

5

Data hold from clock rise

5

Enable low to clock rise

10

Enable high width

10

Clock fall to enable high

20

DATA

CLK

LE

S2434

Figure 4. SPI Input Timing Diagram

Serial Bus Timing

The SPI bus speed is programmable. Timing requirements for the

CLK, DATA, and LE signals are provided in Table 2. A serial data

input timing diagram is shown in Figure 4.

PLL Control Registers (R-Divider and N-Divider)

There are three digital PLL control registers that are used to store

the R-divider and N-divider values: R_DIV, N_DIV1, and N_DIV2.

By default, all registers are 25 bits wide. Bits[20:16] are the

address bits of the registers. The 16 least significant bits (LSBs)

represent the data bits.

Three values are needed to calculate the three PLL dividers: the

VCO divider, D:

D

F

F

RF

VCO





(1)

The VCO divider (equal to 1, 2, 4, or 8) is chosen so that the

by:

D

F

F

STEP

COMP





(2)