ADRF6614-EVALZ datasheet(9/61 Pages) AD

Numer części	ADRF6614-EVALZ

Szczegółowy opis	700 MHz to 3000 MHz, Dual Passive Receive Mixer with Integrated PLL and VCO

PDF	61 Pages

Scroll/Zoom	100%

Producent	AD [Analog Devices]

Strona internetowa	http://www.analog.com

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9 / 61 page

Data Sheet

ADRF6614

Rev. 0 | Page 9 of 61

DIGITAL LOGIC SPECIFICATIONS

Table 7.

Symbol

Description

Min

Typ

Max

Unit

tCLK

Serial clock period

tDS

Setup time between data and rising edge of SCLK

tDH

Hold time between data and rising edge of SCLK

Setup time between falling edge of CS and SCLK

Hold time between rising edge of CS and SCLK

tHIGH

Minimum period for SCLK to be in a logic high state

tLOW

Minimum period for SCLK to be in a logic low state

tACCESS

Maximum delay between falling edge of SCLK and output data Valid for a read operation

231

Maximum delay between CS deactivation and SDIO bus return to high impedance

tDS

tDH

tHIGH

tLOW

tCLK

DON'T CARE

D15

D14

D13

DON'T CARE

SCLK

SDIO

R/W

tACCESS

Figure 2. Setup and Hold Timing Measurements

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