| Zakładka z wyszukiwarką danych komponentów |
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DA7210 Arkusz danych(PDF) 96 Page - Renesas Technology Corp |
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DA7210 Arkusz danych(HTML) 96 Page - Renesas Technology Corp |
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96 / 119 page ![]() DA7210 Ultra-low power stereo codec Datasheet Revision 3.2 23-Dec-2021 CFR0011-120-00 Rev 5 96 of 118 © 2021 Renesas Electronics Table 84: PLL_DIV3 0x2B Bit Mode Symbol Description Reset 7 R Reserved Reserved 0 6 R/W PLL_BYP Bypass PLL 0 = disable (do not disable unless PLL is operational) 1 = enable (PLL bypassed) 0 5:4 R/W MCLK_RANGE MCLK frequency range: 00 = 32.768 kHz 01 = 10-20 MHz 10 = 20-40 MHz 11 = 40-80 MHz 01 3:0 R/W PLL_DIV_L Feedback divider ratio bit [3:0]. Refer to Table 32 and Table 33 for suggested settings. 0000 |
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