DA7210 datasheet(22/119 Pages) RENESAS

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DA7210

Ultra-low power stereo codec

Datasheet

Revision 3.2

23-Dec-2021

CFR0011-120-00 Rev 5

22 of 118

Table 14: Electrical characteristics: Phase locked loop (MCLK)

Parameter

Description

Conditions

Min

Typ

Max

Unit

Input Jitter

cycle to cycle

rms

100

Input Impedance

DC impedance > 10 M

300

0.5

Ω

Interface mode (MCLK is 256 Fs, PLL off)

Fin

Input frequency

256 Fs

128 Fs (96 kHz)

11.289

12.288

MHz

Oscillator mode (MCLK from standard oscillator, PLL on)

Fin

Input frequency

12.0, 13.0, 13.5, 14.4,

19.2, 19.68 MHz (x 1, 2 or

4), 32 kHz mode

32.768

MHz

kHz

I2S tracking range (SRM)

Maximum mismatch of

I2S word-clock

I2S clock drift

Maximum frequency drift

of I2S word clock

ppm/s

VIN AC

MCLK Shaper range

For AC coupling with

internal clock shaping

300

500

1000

mVPP

Table 15: Electrical characteristics: Digital I/O

(Ta = -40 to +85ºC)

Parameter

Description

Conditions

Min

Typ

Max

Unit

VIH

CLK, WCLK, DATIN, SK,

nCS, SI, PD, MCLK,

Input High Voltage

0.7*VDDDIO

VDDDIO

VIL

CLK, WCLK, DATIN, SK,

nCS, SI, PD, MCLK,

Input Low Voltage

-0.3

0.3*VDDDI

VOH @

1 mA

CLK, WCLK, DATOUT

Output High Voltage

0.8*VDDDIO

VDDDIO

VOH

(open drain mode)

Output High Voltage

OPEN

DRAIN

3.6

VOL @

1 mA

CLK, WCLK, DATOUT

Output Low Voltage

0.3

MCLK

Input High Voltage

DC-coupled TTL

signal

0.7*VDDDIO

VDDDIO

MCLK

Input Low Voltage

-0.3

0.3*VDDDI

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