DA7210 datasheet(25/119 Pages) RENESAS

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DA7210

Ultra-low power stereo codec

Datasheet

Revision 3.2

23-Dec-2021

CFR0011-120-00 Rev 5

25 of 118

7.3

Digital audio interface timing - 4-wire control timing

BIT 7

R/W

BIT 1

LSB

BIT 1

Address

R/W

DATA

nCS

Figure 6: 4-wire control timing diagram

Timing shown is valid for active low and active high CS.

Table 18: 4-wire control timing characteristics

(Ta = -40 to +85ºC)

Parameter

Description

Label in plot

Min

Typ

Max

Unit

Cycle time

tCSS

Enable lead time

2, from CS active to first SK edge

tSCS

Enable lag time

3, from last SK edge to CS idle

tCL

Clock low time

0.4 x tC

tCH

Clock high time

0.4 x tC

tSIS

Data In setup time

tSIH

Data In hold time

tSOV

Data Out valid time

tSOH

Data Out hold time

Data access time

tWCS

CS inactive time

Table 19: Start-up times after setting SC_MST_EN = 1

Source

Output

Comment

Min

Typ

Max

Unit

VBG

VBG voltage >90% with 1 µF

VBG capacitor

All analogue inputs and

DACL/R

HPL/R

Slave mode; 200 ms added

delay required

200

All analogue inputs and

DACL/R

HPL/R

32 kHz PLL master mode;

200 ms added delay required

500

All analogue inputs and

DACL/R

OUT1L/R

Slave mode

250

All analogue inputs

ADCL/R

Slave mode

200

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