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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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DA7210 Arkusz danych(PDF) 23 Page - Renesas Technology Corp |
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DA7210 Arkusz danych(HTML) 23 Page - Renesas Technology Corp |
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23 / 119 page  DA7210 Ultra-low power stereo codec Datasheet Revision 3.2 23-Dec-2021 CFR0011-120-00 Rev 5 23 of 118 © 2021 Renesas Electronics 7 Timing characteristics 7.1 Digital audio interface timing - I2S/DSP (in master/slave mode) T tlC thC CLK DATIN tf tsD DATOUT WCLK tr tdCW tdCD tdWD thD tsW thW Figure 4: I2S/DSP timing diagram Table 16: I2S/DSP timing characteristics (Ta = -40 to +85ºC) Parameter Description Conditions Min Typ Max Unit Input impedance DC impedance > 10 MΩ 300 1.0 2.5 Ω pF T CLK period 75 ns tr CLK rise time 8 ns tf CLK fall time 8 ns thC CLK high period 40% 60% T tlC CLK low period 40% 60% T tdCW CLK to WCLK delay -30% +30% T tdCD CLK to DATOUT delay -30% +30% T thW WCLK high time DSP mode 100% T Non-DSP mode Word length T tlW WCLK low time DSP mode 100% T Non-DSP mode Word length T tsW WCLK setup time Slave mode 7 ns thW WCLK hold time Slave mode 2 ns tsD DATIN setup time 7 ns thD DATIN hold time 2 ns tdWD DATOUT to WCLK delay DATOUT is synchronised to CLK |
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