MPC8323ECVRADDC datasheet(34/80 Pages) FREESCALE

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MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

PCI

12 PCI

This section describes the DC and AC electrical specifications for the PCI bus of the MPC8323E.

12.1

PCI DC Electrical Characteristics

Table 35 provides the DC electrical characteristics for the PCI interface of the MPC8323E.

12.2

PCI AC Electrical Specifications

This section describes the general AC timing parameters of the PCI bus of the MPC8323E. Note that the

PCI_CLK or PCI_SYNC_IN signal is used as the PCI input clock depending on whether the MPC8323E

is configured as a host or agent device. Table 36 shows the PCI AC timing specifications at 66 MHz.

Table 35. PCI DC Electrical Characteristics1,2

Parameter

Symbol

Test Condition

Min

Max

Unit

High-level input voltage

VIH

VOUT ≥ VOH (min) or

OVDD + 0.3

Low-level input voltage

VIL

VOUT ≤ VOL (max)

–0.3

0.8

High-level output voltage

VOH

OVDD = min,

IOH = –100 μA

OVDD – 0.2

—

Low-level output voltage

VOL

OVDD = min,

IOL = 100 μA

—0.2

Input current

IIN

0 V

≤ VIN ≤ OVDD

—

±5

μA

Notes:

1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.

2. Ranges listed do not meet the full range of the DC specifications of the

PCI 2.3 Local Bus Specifications.

Table 36. PCI AC Timing Specifications at 66 MHz

Parameter

Symbol1

Min

Max

Unit

Notes

Clock to output valid

tPCKHOV

—6.0

Output hold from clock

tPCKHOX

1—

Clock to output high impedence

tPCKHOZ

—14

2, 3

Input setup to clock

tPCIVKH

3.0

—

2, 4

Input hold from clock

tPCIXKH

0—

2, 4

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH symbolizes PCI timing

(PC) with respect to the time the input signals (I) reach the valid state (V) relative to the PCI_SYNC_IN clock, tSYS, reference

(K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC) with respect to the time hard reset

(R) went high (H) relative to the frame signal (F) going to the valid (V) state.

2. See the timing measurement conditions in the

PCI 2.3 Local Bus Specifications.

3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

4. Input timings are measured at the pin.

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