MPC8323ECVRADDC datasheet(9/80 Pages) FREESCALE

9 / 80 page

MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

Electrical Characteristics

2.1.4

Input Capacitance Specification

Table 4 describes the input capacitance for the CLKIN pin in the MPC8323E.

2.2

Power Sequencing

MPC8323E does not require the core supply voltage and I/O supply voltages to be applied in any particular

order. However, note that during the power ramp up, before the power supplies are stable, there might be

a period of time that I/O pins are actively driven. After the power is stable, as long as PORESET is

asserted, most I/O pins are three-stated. In order to minimize the time that I/O pins being actively driven,

it is recommended to apply core voltage before I/O voltage and assert PORESET before the power supplies

fully ramp up. The core voltage (VDD) should reach its nominal level before the I/O voltage (OVDD and

GVDD) reaches 0.7 V. In addition, the I/O voltage should reach its nominal level within 100 microseconds

after the core voltage has reached its nominal level (see Figure 4). Excessive current consumption may be

observed if these recommendations are not followed.

Figure 4. MPC8323E Power Sequencing

Table 4. Input Capacitance Specification

Parameter/Condition

Symbol

Min

Max

Unit

Notes

Input capacitance for all pins except CLKIN

Input capacitance for CLKIN

CICLKIN

—

Note:

1. The external clock generator should be able to drive 10 pF.

100

μs

Min

Max

0.7 V

Core Voltage (VDD) 1 V

I/O Voltage (GVDD and OVDD) 3.3 V

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