MPC8323ECVRADDC datasheet(47/80 Pages) FREESCALE

47 / 80 page

MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

Package and Pin Listings

Figure 41 provide the AC test load for the USB.

Figure 41. USB AC Test Load

21 Package and Pin Listings

This section details package parameters, pin assignments, and dimensions. The MPC8323E is available in

a thermally enhanced Plastic Ball Grid Array (PBGA); see Section 21.1, “Package Parameters for the

MPC8323E PBGA,” and Section 21.2, “Mechanical Dimensions of the MPC8323E PBGA,” for

information on the PBGA.

21.1

Package Parameters for the MPC8323E PBGA

The package parameters are as provided in the following list. The package type is 27 mm

× 27 mm, 516

PBGA.

Package outline

27 mm

× 27 mm

Interconnects

516

Pitch

1.00 mm

Module height (typical)

2.25 mm

Solder Balls

62 Sn/36 Pb/2 Ag (ZQ package)

95.5 Sn/0.5 Cu/4Ag (VR package)

Ball diameter (typical)

0.6 mm

21.2

Mechanical Dimensions of the MPC8323E PBGA

Figure 42 the mechanical dimensions and bottom surface nomenclature of the MPC8323E, 516-PBGA

package.

Skew among RXP, RXN, and RXD

tUSRPND

—

100

Low speed transitions

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(state)(signal) for receive signals

and t(first two letters of functional block)(state)(signal) for transmit signals. For example, tUSRSPND symbolizes USB timing (US) for the

USB receive signals skew (RS) among RXP, RXN, and RXD (PND). Also, tUSTSPN symbolizes USB timing (US) for the USB

transmit signals skew (TS) between TXP and TXN (PN).

2. Skew measurements are done at OVDD/2 of the rising or falling edge of the signals.

Table 54. USB General Timing Parameters (continued)

Parameter

Symbol1

Min

Max

Unit

Notes

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

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