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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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MPC8323ECVRADDC Arkusz danych(PDF) 65 Page - Freescale Semiconductor, Inc |
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MPC8323ECVRADDC Arkusz danych(HTML) 65 Page - Freescale Semiconductor, Inc |
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65 / 80 page  MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 65 Clocking 22.4 System PLL Configuration The system PLL is controlled by the RCWL[SPMF] parameter. Table 58 shows the multiplication factor encodings for the system PLL. As described in Section 22, “Clocking,” the LBCM, DDRCM, and SPMF parameters in the reset configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 59 shows the expected frequency values for the CSB frequency for select csb_clk to CLKIN/PCI_SYNC_IN ratios. Table 58. System PLL Multiplication Factors RCWL[SPMF] System PLL Multiplication Factor 0000 Reserved 0001 Reserved 0010 × 2 0011 × 3 0100 × 4 0101 × 5 0110 × 6 0111–1111 Reserved |
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