MPC8280 datasheet(24/1386 Pages) FREESCALE

24 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

xxiv

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

Chapter 19

SDMA Channels and IDMA Emulation

19.1

SDMA Bus Arbitration and Bus Transfers .................................................................... 19-2

19.2

SDMA Registers ............................................................................................................ 19-3

19.2.1

SDMA Status Register (SDSR) ................................................................................. 19-3

19.2.2

SDMA Mask Register (SDMR)................................................................................. 19-4

19.2.3

SDMA Transfer Error Address Registers (PDTEA and LDTEA)............................. 19-4

19.2.4

SDMA Transfer Error MSNUM Registers (PDTEM and LDTEM) ......................... 19-4

19.3

IDMA Emulation ........................................................................................................... 19-5

19.4

IDMA Features .............................................................................................................. 19-5

19.5

IDMA Transfers ............................................................................................................. 19-6

19.5.1

Memory-to-Memory Transfers .................................................................................. 19-6

19.5.1.1

External Request Mode.......................................................................................... 19-8

19.5.1.2

Normal Mode......................................................................................................... 19-9

19.5.1.3

Working with a PCI Bus ........................................................................................ 19-9

19.5.2

Memory to/from Peripheral Transfers ....................................................................... 19-9

19.5.2.1

Dual-Address Transfers ....................................................................................... 19-10

19.5.2.1.1

Peripheral to Memory ...................................................................................... 19-10

19.5.2.1.2

Memory to Peripheral ...................................................................................... 19-10

19.5.2.2

Single Address (Fly-By) Transfers ...................................................................... 19-10

19.5.2.2.1

Peripheral-to-Memory Fly-By Transfers ......................................................... 19-11

19.5.2.2.2

Memory-to-Peripheral Fly-By Transfers ......................................................... 19-11

19.5.3

Controlling 60x Bus Bandwidth .............................................................................. 19-11

19.5.4

PCI Burst Length and Latency Control ................................................................... 19-12

19.6

IDMA Priorities ........................................................................................................... 19-12

19.7

IDMA Interface Signals ............................................................................................... 19-13

19.7.1

DREQx and DACKx ............................................................................................... 19-13

19.7.1.1

Level-Sensitive Mode .......................................................................................... 19-14

19.7.1.2

Edge-Sensitive Mode........................................................................................... 19-14

19.7.2

DONEx .................................................................................................................... 19-14

19.8

IDMA Operation .......................................................................................................... 19-14

19.8.1

Auto Buffer and Buffer Chaining ............................................................................ 19-15

19.8.2

IDMAx Parameter RAM ......................................................................................... 19-16

19.8.2.1

DMA Channel Mode (DCM)............................................................................... 19-18

19.8.2.2

Data Transfer Types as Programmed in DCM..................................................... 19-20

19.8.2.3

Programming DTS and STS ................................................................................ 19-20

19.8.3

IDMA Performance ................................................................................................. 19-22

19.8.4

IDMA Event Register (IDSR) and Mask Register (IDMR) .................................... 19-22

19.8.5

IDMA BDs............................................................................................................... 19-23

19.9

IDMA Commands........................................................................................................ 19-26

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