MPC8280 datasheet(55/1386 Pages) FREESCALE

55 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

Figures

Figure

Number

Title

Page

Number

11-61

RAM Array and Signal Generation .................................................................................... 11-71

11-62

The RAM Word................................................................................................................... 11-71

11-63

CS Signal Selection............................................................................................................. 11-76

11-64

BS Signal Selection............................................................................................................. 11-76

11-65

UPM Read Access Data Sampling...................................................................................... 11-79

11-66

Wait Mechanism Timing for Internal and External Synchronous Masters ......................... 11-80

11-67

DRAM Interface Connection to the 60x Bus (64-Bit Port Size) ........................................ 11-82

11-68

Single-Beat Read Access to FPM DRAM .......................................................................... 11-84

11-69

Single-Beat Write Access to FPM DRAM ......................................................................... 11-85

11-70

Burst Read Access to FPM DRAM (No LOOP) ................................................................ 11-86

11-71

Burst Read Access to FPM DRAM (LOOP) ...................................................................... 11-87

11-72

Burst Write Access to FPM DRAM (No LOOP)................................................................ 11-88

11-73

Refresh Cycle (CBR) to FPM DRAM ................................................................................ 11-89

11-74

Exception Cycle .................................................................................................................. 11-90

11-75

FPM DRAM Burst Read Access (Data Sampling on Falling Edge of CLKIN)................. 11-92

11-76

MPC8280/EDO Interface Connection to the 60x Bus ........................................................ 11-93

11-77

Single-Beat Read Access to EDO DRAM .......................................................................... 11-94

11-78

Single-Beat Write Access to EDO DRAM ......................................................................... 11-95

11-79

Single-Beat Write Access to EDO DRAM Using REDO to Insert Three

Wait States ...................................................................................................................... 11-96

11-80

Burst Read Access to EDO DRAM .................................................................................... 11-97

11-81

Burst Write Access to EDO DRAM ................................................................................... 11-98

11-82

Refresh Cycle (CBR) to EDO DRAM ................................................................................ 11-99

11-83

Exception Cycle For EDO DRAM ................................................................................... 11-100

11-84

Pipelined Bus Operation and Memory Access in 60x-Compatible Mode ........................ 11-104

11-85

External Master Access (GPCM)...................................................................................... 11-105

11-86

External Master Configuration with SDRAM Device ...................................................... 11-106

12-1

L2 Cache in Copy-Back Mode.............................................................................................. 12-2

12-2

External L2 Cache in Write-Through Mode ......................................................................... 12-4

12-3

External L2 Cache in ECC/Parity Mode............................................................................... 12-6

12-4

Read Access with L2 Cache.................................................................................................. 12-8

13-1

Test Logic Block Diagram .................................................................................................... 13-2

13-2

TAP Controller State Machine .............................................................................................. 13-3

13-3

Output Pin Cell (O.Pin)......................................................................................................... 13-4

13-4

Observe-Only Input Pin Cell (I.Obs) .................................................................................... 13-4

13-5

Output Control Cell (IO.CTL) .............................................................................................. 13-5

13-6

General Arrangement of Bidirectional Pin Cells .................................................................. 13-5

14-1

CPM Block Diagram............................................................................................................. 14-3

14-2

Communications Processor (CP) Block Diagram................................................................. 14-6

14-3

RISC Controller Configuration Register (RCCR.................................................................. 14-9

14-4

RISC Time-Stamp Control Register (RTSCR) ................................................................... 14-11

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