MPC8280 datasheet(46/1386 Pages) FREESCALE

46 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

xlvi

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

39.5.1

Receive/Transmit Function Code Registers (RFCR/TFCR).................................... 39-12

39.6

SPI Commands ............................................................................................................ 39-12

39.7

The SPI Buffer Descriptor (BD) Table ........................................................................ 39-13

39.7.1

SPI Buffer Descriptors (BDs) .................................................................................. 39-13

39.7.1.1

SPI Receive BD (RxBD) ..................................................................................... 39-14

39.7.1.2

SPI Transmit BD (TxBD) .................................................................................... 39-15

39.8

SPI Master Programming Example ............................................................................. 39-16

39.9

SPI Slave Programming Example................................................................................ 39-17

39.10

Handling Interrupts in the SPI ..................................................................................... 39-17

Chapter 40

I2C Controller

40.1

Features .......................................................................................................................... 40-2

40.2

I2C Controller Clocking and Signal Functions .............................................................. 40-2

40.3

I2C Controller Transfers ................................................................................................ 40-2

40.3.1

I2C Master Write (Slave Read).................................................................................. 40-3

40.3.2

I2C Loopback Testing................................................................................................ 40-4

40.3.3

I2C Master Read (Slave Write).................................................................................. 40-4

40.3.4

I2C Multi-Master Considerations .............................................................................. 40-5

40.4

I2C Registers .................................................................................................................. 40-5

40.4.1

I2C Mode Register (I2MOD) .................................................................................... 40-6

40.4.2

I2C Address Register (I2ADD) ................................................................................. 40-7

40.4.3

I2C Baud Rate Generator Register (I2BRG) ............................................................. 40-7

40.4.4

I2C Event/Mask Registers (I2CER/I2CMR) ............................................................. 40-7

40.4.5

I2C Command Register (I2COM) ............................................................................. 40-8

40.5

I2C Parameter RAM....................................................................................................... 40-9

40.6

I2C Commands............................................................................................................. 40-11

40.7

The I2C Buffer Descriptor (BD) Table ........................................................................ 40-11

40.7.1

I2C Buffer Descriptors (BDs).................................................................................. 40-12

40.7.1.1

I2C Receive Buffer Descriptor (RxBD) .............................................................. 40-12

40.7.1.2

I2C Transmit Buffer Descriptor (TxBD) ............................................................. 40-13

Chapter 41

Parallel I/O Ports

41.1

Features .......................................................................................................................... 41-1

41.2

Port Registers ................................................................................................................. 41-1

41.2.1

Port Open-Drain Registers (PODRA–PODRD) ........................................................ 41-2

41.2.2

Port Data Registers (PDATA–PDATD) ..................................................................... 41-2

41.2.3

Port Data Direction Registers (PDIRA–PDIRD)....................................................... 41-3

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