MPC8280 datasheet(53/1386 Pages) FREESCALE

53 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

liii

Figures

Figure

Number

Title

Page

Number

9-75

Outbound Message Interrupt Status Register (OMISR) ....................................................... 9-80

9-76

Outbound Message Interrupt Mask Register (OMIMR)....................................................... 9-81

9-77

Inbound Message Interrupt Status Register (IMISR)............................................................ 9-82

9-78

Inbound Message Interrupt Mask Register (IMIMR) ........................................................... 9-83

9-79

Messaging Unit Control Register (MUCR) .......................................................................... 9-84

9-80

Queue Base Address Register (QBAR) ................................................................................ 9-85

9-81

DMA Controller Block Diagram .......................................................................................... 9-86

9-82

DMA Mode Registers 0–3 (DMAMRx) ............................................................................... 9-89

9-83

DMA Status Registers 0–3 (DMASRx) ................................................................................ 9-91

9-84

DMA Current Descriptor Address Registers 0–3 (DMACDARx) ....................................... 9-92

9-85

DMA Source Address Registers 0–3 (DMASARx).............................................................. 9-93

9-86

DMA Destination Address Registers 0–3 (DMADARx)...................................................... 9-94

9-87

DMA Byte Count Registers 0–3 (DMABCRx) .................................................................... 9-95

9-88

DMA Next Descriptor Address Registers 0–3 (DMANDARx)............................................ 9-95

9-89

DMA Chain of Segment Descriptors .................................................................................... 9-97

10-1

MPC8280 System Clock Architecture .................................................................................. 10-3

10-2

PCI Bridge as an Agent, Operating from the PCI System Clock ......................................... 10-4

10-3

PCI Bridge as a Host, Generating the PCI System Clock..................................................... 10-5

10-4

PLL Filtering Circuit............................................................................................................. 10-5

10-5

System Clock Control Register (SCCR) ............................................................................... 10-6

10-6

System Clock Mode Register (SCMR) ................................................................................. 10-7

11-1

Dual-Bus Architecture .......................................................................................................... 11-2

11-2

Memory Controller Machine Selection................................................................................. 11-5

11-3

Simple System Configuration ............................................................................................... 11-6

11-4

Basic Memory Controller Operation..................................................................................... 11-7

11-5

Partial Data Valid for 32-Bit Port Size Memory, Double-Word Transfer ............................11-11

11-6

Base Registers (BRx) .......................................................................................................... 11-13

11-7

Option Registers (ORx)—SDRAM Mode .......................................................................... 11-15

11-8

ORx —GPCM Mode........................................................................................................... 11-17

11-9

ORx—UPM Mode .............................................................................................................. 11-19

11-10

60x/Local SDRAM Mode Register (PSDMR/LSDMR) .................................................... 11-20

11-11

Machine x Mode Registers (MxMR) .................................................................................. 11-26

11-12

Memory Data Register (MDR) ........................................................................................... 11-29

11-13

Memory Address Register (MAR)...................................................................................... 11-29

11-14

60x Bus-Assigned UPM Refresh Timer (PURT)................................................................ 11-30

11-15

Local Bus-Assigned UPM Refresh Timer (LURT)............................................................. 11-30

11-16

60x Bus-Assigned SDRAM Refresh Timer (PSRT) ........................................................... 11-31

11-17

Local Bus-Assigned SDRAM Refresh Timer (LSRT)........................................................ 11-32

11-18

Memory Refresh Timer Prescaler Register (MPTPR) ........................................................ 11-32

11-19

128-Mbyte SDRAM (Eight-Bank Configuration, Banks 1 and 8 Shown) ......................... 11-34

11-20

PRETOACT = 2 (2 Clock Cycles)...................................................................................... 11-39

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