MPC8280 datasheet(37/1386 Pages) FREESCALE

37 / 1386 page

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

xxxvii

Contents

Paragraph

Number

Title

Page

Number

31.10.5.10

AAL5 TxBDs....................................................................................................... 31-74

31.10.5.11

AAL1 TxBDs....................................................................................................... 31-75

31.10.5.12

AAL0 TxBDs....................................................................................................... 31-76

31.10.5.13

AAL1 CES TxBDs .............................................................................................. 31-77

31.10.5.14

AAL2 TxBDs....................................................................................................... 31-77

31.10.5.15

AAL5, AAL1 User-Defined Cell—TxBD Extension.......................................... 31-77

31.10.6

AAL1 Sequence Number (SN) Protection Table..................................................... 31-77

31.10.7

UNI Statistics Table ................................................................................................. 31-78

31.11

ATM Exceptions .......................................................................................................... 31-79

31.11.1

Interrupt Queues ...................................................................................................... 31-79

31.11.2

Interrupt Queue Entry .............................................................................................. 31-80

31.11.3

Interrupt Queue Parameter Tables ........................................................................... 31-80

31.12

The UTOPIA Interface ................................................................................................ 31-81

31.12.1

UTOPIA Interface Master Mode ............................................................................. 31-81

31.12.1.1

UTOPIA Master Multiple PHY Operation.......................................................... 31-82

31.12.2

UTOPIA Interface Slave Mode ............................................................................... 31-83

31.12.2.1

UTOPIA Slave Multiple PHY Operation ............................................................ 31-84

31.12.2.2

UTOPIA Clocking Modes ................................................................................... 31-84

31.12.2.3

UTOPIA Loop-Back Modes ................................................................................ 31-84

31.12.3

Extended Number of PHYs ..................................................................................... 31-85

31.13

ATM Registers ............................................................................................................. 31-85

31.13.1

General FCC Mode Register (GFMR)..................................................................... 31-85

31.13.2

FCC Protocol-Specific Mode Register (FPSMR).................................................... 31-85

31.13.3

ATM Event Register (FCCE)/Mask Register (FCCM)............................................ 31-88

31.14

ATM Transmit Command ............................................................................................ 31-89

31.15

Transmission Rate Modes—External, Internal, and Expanded Internal...................... 31-90

31.15.1

FCC Transmit Internal Rate Mode .......................................................................... 31-91

31.15.1.1

FCC Transmit Internal Rate Register (FTIRRx) ................................................. 31-91

31.15.1.2

Example ............................................................................................................... 31-92

31.15.1.3

Internal Rate Programming Model ...................................................................... 31-93

31.15.1.4

FCC Transmit Internal Rate Port Enable Registers (FIRPERx).......................... 31-93

31.15.1.5

FCC Internal Rate Event Registers (FIRERx) ..................................................... 31-94

31.15.1.6

FCC Internal Rate Selection Registers (FIRSRx_HI, FIRSRx_LO) ................... 31-95

31.16

SRTS Generation and Clock Recovery Using External Logic .................................... 31-97

31.17

Configuring the ATM Controller for Maximum CPM Performance ........................... 31-98

31.17.1

Using Transmit Internal Rate Mode ........................................................................ 31-98

31.17.2

APC Configuration .................................................................................................. 31-99

31.17.3

Buffer Configuration................................................................................................ 31-99

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