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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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STLC5464 Arkusz danych(PDF) 72 Page - STMicroelectronics |
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STLC5464 Arkusz danych(HTML) 72 Page - STMicroelectronics |
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72 / 83 page  PRIORITY 5 is the last priority for DRAM Refresh if validated. DRAM Refresh obtains PRIORITY 0 (the first priority) automatically when the first half cycle is spend without access to memory. After reset (E400)H, the Rx DMA Controller has the PRIORITY 1 the Microprocessor has the PRIORITY 2 the Tx DMA Controller has the PRIORITY 3 the Interrupt Controller has the PRIORITY 4 the DRAM Refresh has the PRIORITY 5 VIII.27 - Initiate Block Address Register - IBAR (34)H bit15 bit8 bit7 bit 0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 After reset (0000)H A8/23 : Address bits. These 16 bits are the segment address bits of the Initiate Block (A8 to A23 for the external memory).The offset is zero (A0 to A7 =”0”). The Initiate Block Address (IBA) is : 23 87 0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 0000 000 0 The 23 more significant bits define one of 8 Megawords. (One word comprises two bytes.) The least significant bit defines one of two bytes when the microprocessor selects one byte. VIII.28 - Interrupt Queue Size Register - IQSR (36)H bit15 bit8 bit7 bit 0 r e s e r v e d HS2 HS1 HS0 MS2 MS1 MS0 CS1 CS0 After reset (0000)H CS0/1 : Command/Indicate Interrupt Queue Size These two bits define the size of Command/Indicate Interrupt Queue in external memory. The location is IBA + 256 + HDLC Queue size + Monitor Channel Queue Size (see The Initiate Block Address (IBA)). MS0/2 : Monitor Channel Interrupt Queue Size These three bits define the size of Monitor Channel Interrupt Queue in external memory. The location is IBA + 256 + HDLC Queue size. HS0/2 : HDLC Interrupt Queue Size These three bits define the size of HDLC status Interrupt Queue in external memory for each channel. The location is IBA+256 (see The Initiate Block Address (IBA)) HS2 HS1 HS0 HDLC Queue Size MS2 MS1 MS0 MON Queue Size CS1 CS0 C/I Queue Size 0 0 0 128 words 0 0 0 128 words 0 0 64 words 0 0 1 256 words 0 0 1 256 words 0 1 128 words 0 1 0 384 words 0 1 0 384 words 1 0 192 words 0 1 1 512 words 0 1 1 512 words 1 1 256 words 1 0 0 640 words 1 0 0 640 words 1 0 1 768 words 1 0 1 768 words 1 1 0 896 words 1 1 0 896 words 1 1 1 1024 words 1 1 1 1024 words VIII - INTERNAL REGISTERS (continued) STLC5464 72/83 |
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