STLC5464 datasheet(33/83 Pages) STMICROELECTRONICS

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III - FUNCTIONAL DESCRIPTION (continued)

NRAS0

NRAS1

DM8/15

DM0/7

4M x 16

NCAS 1

NCAS 0

ADM0/10, NWE, NOE a re conne cte d to e a ch circuit

Figure 22 : 4M x 16 DRAM Circuit Organization

NRAS3

NRAS2

NRAS0

NRAS1

DM8/15

DM0/7

1M x 16

NCAS1

NCAS0

ADM0/9, NWE, NOE a re conne cted to e a ch circuit

Figure 21 : 1M x 16 DRAM Circuit Organization

µP

MHDLC 0

RAM

µP Bus

RAM Bus

TR O

TR I

MHDLC 1

TR O

TR I

MHDLC n

TR O

TR I

Figure 23 : Chain of n

Multi-HDLC Components

III.5.5.2 - 1M x n DRAM Signals

Signals

A22

A20

A0 or equiv.

NRAS3

NRAS2

NRAS1

NRAS0

NCAS1

NCAS0

The Address bits delivered by the

Multi-HDLC for

1M x n DRAM circuits are :

ADM0/9 (2 x 10 = 18 bits) correspondingwith A1/20

delivered by the

µP.

III.5.5.3 - 4M x n DRAM Signals

Signals

A23

A0 or equiv.

NRAS1

NRAS0

NCAS1

NCAS0

The Address bits delivered by the

Multi-HDLC for

4M x n DRAM circuits are :

ADM0/10 (2 x 11 = 22 bits) corresponding with

A1/22 delivered by the

µP.

III.6 - Bus Arbitration

The Bus arbitration function arbitrates the access

to the bus between different entities of the circuit.

Those entities which can call for the bus are the

following :

- The receive DMA controller,

- The microprocessor,

- The transmit DMA controller,

- The Interrupt controller,

- The memory interface for refreshing the DRAM.

This list gives the memory access priorities per

default.

If the treatment of more than 32 HDLC channels is

required by the application, it is possible to chain

several

Multi-HDLC components.That is done with

two external pins (TRI, TRO) and a token ring

system.

The TRI, TRO signals are managed by the bus

arbitration function too. When a chip has finished

its tasks, it sends a pulse of 30 ns to the next chip.

STLC5464

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