STLC5464 datasheet(14/83 Pages) STMICROELECTRONICS

14 / 83 page

Pseudo

Random

Sequence

Generator

COUNTER

XTAL

WATCHDOG

µP

INTERFACE

CLOCK

SELECTION

RAM

INTERFACE

VCX OUT

XTAL1

XTAL2

DIN8

WDO

GCI1

GCI0

Pseudo

Random

Sequence

Analyser

SWITCHING MATRIX

n x 64 kb/s

GCI0

GCI1

FSCV*

FSCG

DCLK

Internal

Circuit

16 FS

5CB

TIME SLOT ASSIGNER FOR MULTIHDLC

GCI CHANNEL DEFINITION

V10

32 Rx HDLC

with Adress

Recognition

32 Rx DMAC

16 Rx

C/I

16 Rx

MON

16 Tx

C/I

16 Tx

MON

6EC

32 Tx HDLC

with CSMA CR

for Content. Bus

32 Tx DMAC

µP Bus

INTERRUPT

CONTROLLER

C/I

MON

C/I

MON

RAM

Bus

49 INT0

50 INT1

Internal Bus

BUS ARBITRATION

STLC5464

V10

VCX IN

DIN7

DIN6

Figure 1 : General Block Diagram

II - BLOCK DIAGRAM

The top level functionalities of

Multi-HDLC appear on the general block diagram.

There are :

- The switching matrix,

- The time slot assigner,

- The 32 HDLC transmitters with associated DMA

controllers,

- The 32 HDLC receivers with associated DMA

controllers,

- The 16 Command/Indicate and Monitor Channel

transmitters belonging to two General Compo-

nent Interfaces(GCI),

- The 16 Command/Indicate and Monitor Channel

receivers belonging to two General Component

Interfaces (GCI),

- The memory interface,

- The microprocessor interface,

- The bus arbitration,

- The clock selection and time synchronization

function,

- The interrupt controller,

- The watchdog,

STLC5464

14/83

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