STLC5464 datasheet(34/83 Pages) STMICROELECTRONICS

34 / 83 page

III - FUNCTIONAL DESCRIPTION (continued)

III.7 - Clock Selection and Time Synchronization

III.7.1 - Clock Distribution Selection

and Supervision

Two clock distributions are available : Clock at

4.096MHzor 8.192MHz and a synchronization sig-

nal at 8kHz. The component has to select one of

these two distributions and to check its integrity

(see Figure 25 and Paragraph ”General Configura-

tion Register GCR (02)H” on Page 57).

DCLK, FSCGCI and FSCV* are output on three

external pins of the

Multi-HDLC. DCLK is the clock

selected between Clock A and Clock B. FSCGCI

and FSCV* are functions of the selected distribu-

tion and respect the GCI and V* frame synchroni-

zation specifications.

The supervision of the clock distribution consists of

verifying its availability. The detection of the clock

absence is done in less than 250

µs. In case the

clock is absent, an interrupt is generated with a

4kHz recurrence. Then the clock distribution is

switched by the microprocessor. This change of

clock occurs on a falling edge of the new selected

distribution.

Depending on the applications, three different sig-

nals of synchronization (GCI, V* or Sy) can be

provided to the component. The clock A/B fre-

quency can be a 4096 or 8192kHz clock. The

component is informed of the synchronization and

clocks that are connected by software.The timings

of the different synchronization are given Page 38.

III.7.2 - VCXO Frequency Synchronization

An external VCXO can be used to provide a clock

to the transmission components. This clock is con-

trolled by the main clock distribution (Clock A or

Clock B at 4096kHz). As the clock of the transmis-

sion component is 15360 or 16384kHz,a configur-

able function is necessary.

The VCXO frequency is divided by P (30 or 32) to

provide a common sub-multiple (512kHz) of the

reference frequency CLOCKA or CLOCKB

(4096kHz). The comparison of these two signals

gives an error signal which commands the VCXO.

Two external pins are needed to perform this func-

tion : VCXO-IN and VCXO-OUT (see Figure 26 on

Page 35).

CLOCK B

FRAME B

CLOCK A

FS CV*

FS CGCI

DCLK

To the interna l

MHDLC

Fra me

Clock

RE F. CLOCK

RE S ET

INT1

HCL

Clock

S upervision

De a ctivation

(CS D)

Aor B

Se lecte d

(BS EL)

Select A or B

(S ELB)

CLOCK S ELECTION

At RES ET

FRAME A a nd CLOCK A

a re s elected

Clock Lack

De te ction

from 250

µs

CLOCK

ADAP TATION

SYN0

S YN1

GENERAL CONFIGURATION REGISTER (GCR)

FRAME A

Figure 24 : MHDLC Clock Generation

STLC5464

34/83

STLC5464 Arkusz danych(PDF) 34 Page - STMicroelectronics

STLC5464 Arkusz danych(HTML) 34 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

Arkusz danych Pobierz

Link URL