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STLC5464 Arkusz danych(PDF) 2 Page - STMicroelectronics

Numer części STLC5464
Szczegółowy opis  MULTI-HDLCWITH n x 64 SWITCHING MATRIX ASSOCIATED
PDF  83 Pages
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Producent  STMICROELECTRONICS [STMicroelectronics]
Strona internetowa  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STLC5464 Arkusz danych(HTML) 2 Page - STMicroelectronics

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CONTENTS
Page
I
PIN INFORMATION . . . . ...... ... . . . . . . . . . . . . . . . . ..... ..... ..... .... . . ..
8
I.1
PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . ..... ..... ..... . . . . .. ... . . ...
8
I.2
PIN DESCRIPTION . . . . ...... ... . . . . . . . . . . . . . . . . ..... ..... ..... .... . . ..
9
I.3
PIN DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . ..... ..... . . . . .. ... . . .... ..
13
I.3.1
Input Pin Definition . .... . . . ... ..... ...... .. .. . . . . . .... . . .. . . .... . . ... .. .
13
I.3.2
Output Pin Definition . . . . . . . . . . . . . . . . . . . . . . ..... ..... ..... . . . . .. ... . . ...
13
I.3.3
Input/Output Pin Definition . .... . . . ... ..... ... . . .... . . .. . . .... . . .. . . .... . .
13
II
BLOCK DIAGRAM . . . . ...... ... . . . . . . . . . . . . . . . . ..... ..... ..... .... . . ..
14
III
FUNCTIONAL DESCRIPTION . . . . ...... ... ..... . . ... .. . . . . ..... ..... ....
15
III.1
THE SWITCHING MATRIX N x 64 KBits/S . . . . . . . . . ..... .... . . ... .. . . . . .....
15
III.1.1
Function Description . . . . . . . . . . . . . . . . . . . . . . ..... ..... ..... . . . . .. ... . . ...
15
III.1.2
Architecture of the Matrix . . . . . . . . . . . . . . . . . . . . . . . .... ..... ..... . . . . .. ... . .
15
III.1.3
Connection Function . . . . . . . . . . . . . . . . . . . . . . ..... ..... ..... . . . . .. ... . . ...
15
III.1.4
Loop Back Function . . . . ...... ... . . . . . . . . . . . . . . . . ..... ..... ..... .... . . ..
15
III.1.5
Delay through the Matrix . . . . . . . . . . . . . . . . . . . . . . . .... ..... ..... . . . . .. ... . .
17
III.1.5.1
Variable Delay Mode . . . . ...... ... . . . . . . .... .. . . . . ..... ..... ..... .... .
17
III.1.5.2
Sequence Integrity Mode . . . . ...... ... . . . . . . . ... .. . . . . ..... ..... ..... ..
17
III.1.6
Connection Memory . . . . ...... ... . . . . . . . . . . . . . . . . ..... ..... ..... .... . . ..
21
III.1.6.1
Description . . . . . . . . . . . . . . . . . . . . . . . . .... .... ..... . . . . .. ... . . .... .. . . .
21
III.1.6.2
Access to Connection Memory . . . . . . . . . . . . .... . . ... . . .... ..... ..... . . . . .
21
III.1.6.3
Access to Data Memory . .... . . . ... ..... ... . . .... . . .. . . .... . . .. . . .... . .
21
III.2
HDLC CONTROLLER . .... . . . ... ..... ..... .... . . .. . . .... . . .. . . .... . . ...
21
III.2.1
Function description . . . . ...... ... . . . . . . . . . . . . . . . . ..... ..... ..... .... . . ..
21
III.2.1.1
Format of the HDLC Frame . .... . . . ... .... . . .. . . .... . . .. . . .... . . .. . . ...
21
III.2.1.2
Composition of an HDLC Frame . . . . ...... . . .. .... . . ... .. . . . . ..... ..... .
21
III.2.1.3
Description and Functions of the HDLC Bytes . . . . . . . . . . . . . . . . . . . . . . . .... ...
23
III.2.2
CSMA/CR Capability . . . . . . . . . . . . . . . . . . . . . . ..... ..... ..... . . . . .. ... . . ...
23
III.2.3
Time Slot Assigner Memory . . . . ...... ... . . . . . . . ... .. . . . . ..... ..... ..... ..
24
III.2.4
Data Storage Structure . . . . ...... ... . . . . . . .... .. . . . . ..... ..... ..... .... .
24
III.2.4.1
Reception . . . . ...... ... . . . . . . . . ... ..... ..... ..... ..... .... . . ... . . ...
24
III.2.4.2
Transmission . . . . ...... ... . . . . . . . . ... ... . . ..... ..... ..... .... . . ... . .
24
III.2.4.3
Frame Relay . .... . . . ... ..... ...... .. . . ... . . .... . . .. . . .... . . ... .. . . ..
24
III.2.5
Transparent Modes . . . . ...... ... . . . . . . . . . . . . . . . . ..... ..... ..... .... . . ..
26
III.2.6
Command of the HDLC Channels . .... . . . ... . . .. . . .. . . .... . . .. . . .... . . .. . .
26
III.2.6.1
Reception Control . . . . ...... ... . . . . . . . . . . . . . . . . ..... ..... ..... .... . . ..
26
III.2.6.2
Transmission Control . . . . ...... ... . . . . . . .... .. . . . . ..... ..... ..... .... .
26
III.3
C/I AND MONITOR . . . . ...... ... . . . . . . . . . . . . . . . . ..... ..... ..... .... . . ..
26
III.3.1
Function Description . . . . . . . . . . . . . . . . . . . . . . ..... ..... ..... . . . . .. ... . . ...
26
III.3.2
GCI and V* Protocol . . . . ...... ... . . . . . . . . . . . . . . . . ..... ..... ..... .... . . ..
27
III.3.3
Structure of the Treatment . .... . . . ... ..... ... . . .... . . .. . . .... . . .. . . .... . .
27
III.3.4
CI and Monitor Channel Configuration . .... . . . . . ..... . . .. . . .... . . .. . . .... . . .
27
III.3.5
CI and Monitor Transmission/Reception Command . . . . . . . . . . . . . . . . . . . . . . . ....
27
III.4
MICROPROCESSOR INTERFACE . . . . ...... . . .. .... . . ... .. . . . . ..... ..... .
28
III.4.1
Description . .... . . . ... ..... ...... .. . . .... ..... . . .. . . .... . . ... .. . . .. ...
28
III.4.2
Definition of the Interface for the different microprocessors . . . . . . . . . ..... .... . . ..
28
STLC5464
2/83



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