STLC5464 datasheet(21/83 Pages) STMICROELECTRONICS

21 / 83 page

III.1.6 - Connection Memory

III.1.6.1 - Description

The connection memory is composed of 256 loca-

tions addressed by the number of OTDM and TS

(8x32).

Each location permits :

- to connect each input time slot to one output time

slot (If two or more output time slots are con-

nected to the same input time slot number, there

is broadcasting).

- to select the variable delay mode or the sequence

integrity mode for any time slot.

- to loop back an output time slot. In this case the

contents of an input time slot (ITSx, ITDMp) is the

same as the output time slot (OTSx,OTDMp).

- to output the contents of the corresponding con-

nection memory instead of the data which has

been stored in data memory.

- to output the sequence of the pseudo random

sequence generator on an output time slot: a

pseudo random sequence can be inserted in one

or several time slots (hyperchannel) of the same

Output TDM ; this insertion must be enabled by

the microprocessor in the configuration register

of the matrix.

- to define the source of a sequenceby the pseudo

random sequence analyzer: a pseudo random

sequence can be extracted from one or several

time slots (hyperchannel)of the same Input TDM

and routed to the analyzer; this extraction can be

enabled by the microprocessor in the configura-

tion register of the matrix (SMCR).

- to assert a high impedance level on an output

time slot (disconnection).

- to deliver a programmable 256-bit sequence dur-

ing 125 microsecondson the Programmable syn-

chronization Signal pin (PSS).

III.1.6.2 - Access to Connection Memory

Supposing that the Switching Matrix Configuration

microprocessor, it is possible to access to the con-

nection memory from microprocessor with the help

of two registers :

- Connection Memory Data Register (CMDR) and

- Connection Memory Address Register (CMAR).

III.1.6.3 - Access to Data Memory

To extract the contents of the data memory it is

possible to read the data memory from microproc-

essor with the help of the two registers :

- Connection Memory Data Register (CMDR) and

- Connection Memory Address Register (CMAR).

III.2 - HDLC Controller

III.2.1 - Function Description

The internal HDLC controller can run up to 32

channels in a conventional HDLC mode or in a

transparent (non-HDLC) mode (configurable per

channel).

Each channel bit rate is programmable from 4kbit/s

to 64kbit/s. All the configurations are also possible

from 32 channels (from 4 to 64 kbit/s) to one

channel at 2 Mbit/s.

In reception,the HDLC time slots can directly come

from the input TDM DIN8 (direct HDLC Input) or

from any other TDM input after switching towards

the output 7 of the matrix (configurable per time

slot).

In transmission, the HDLC frames are sent on the

output DOUT6 and on the output CB (with or with-

out contention mechanism), or are switched to-

wards the other TDM output via the input 7 of the

matrix (see Figure 8 on Page 22 and Paragraph

III.2.2 on Page 23).

III.2.1.1 - Format of the HDLC Frame

The format of an HDLC frame is the same in receive

and transmit direction and shown here after.

III.2.1.2 - Composition of an HDLC Frame

Opening Flag

Address Field (first byte)

Address Field (second byte)

Command Field (first byte)

Command Field (second byte)

Data (first byte)

Data (optional)

Data (last byte)

FCS (first byte)

FCS (second byte)

Closing Flag

- Opening Flag

- One or two bytes for address recognition (recep-

tion) and insertion (transmission)

- Data bytes with bit stuffing

- Frame Check Sequence: CRC with polynomial

G(x) = x16 +x12+x5+1

- Closing Flag.

III - FUNCTIONAL DESCRIPTION (continued)

STLC5464

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