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SC667201MMG3 Arkusz danych(PDF) 49 Page - Freescale Semiconductor, Inc |
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SC667201MMG3 Arkusz danych(HTML) 49 Page - Freescale Semiconductor, Inc |
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49 / 120 page ![]() MPC5642A Microcontroller Data Sheet, Rev. 3.1 Freescale Semiconductor 49 Pinout and signal description 2.5 Signal details Table 4. Pad types Pad Type Name I/O Voltage Range Slow pad_ssr_hv 3.0V - 5.5 V Medium pad_msr_hv 3.0 V - 5.5 V Fast pad_fc 3.0 V - 3.6 V MultiV1,2 1 Multivoltage pads are automatically configured in low swing mode when a JTAG or Nexus function is selected, otherwise they are high swing. 2 VDDEH7 supply cannot be below 4.5 V when in low-swing mode. pad_multv_hv 3.0 V - 5.5 V (high swing mode) 3.0 V - 3.6 V (low swing mode) Analog pad_ae_hv 0.0 - 5.5 V LVDS pad_lo_lv — Table 5. Signal details Signal Module or function Description CLKOUT Clock Generation MPC5642A clock output for the calibration bus interface ENGCLK Clock Generation Clock for external ASIC devices EXTAL Clock Generation Input pin for an external crystal oscillator or an external clock source based on the value driven on the PLLREF pin at reset PLLREF Clock Generation Reset/Configuration PLLREF is used to select whether the oscillator operates in xtal mode or external reference mode from reset. PLLREF = 0 selects external reference mode. On the 324 TEPBGA package, PLLREF is bonded to the ball used for PLLCFG[0] for compatibility with MPC55xx devices. For the 176-pin QFP and 208-ball BGA packages: 0: External reference clock is selected 1: XTAL oscillator mode is selected For the 324-ball BGA package: If RSTCFG is 0: 0: External reference clock is selected 1: XTAL oscillator mode is selected If RSTCFG is 1, XTAL oscillator mode is selected. XTAL Clock Generation Crystal oscillator input DSPI_B_SCK_LVDS DSPI_B_SCK_LVDS+ DSPI LVDS pair used for DSPI_B TSB mode transmission DSPI_B_SOUT_LVDS DSPI_B_SOUT_LVDS+ DSPI LVDS pair used for DSPI_B TSB mode transmission |
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