SC667201MMG3 datasheet(10/120 Pages) FREESCALE

10 / 120 page

MPC5642A Microcontroller Data Sheet, Rev. 3.1

Freescale Semiconductor

Introduction

•

Calibration support allowing an external tool to modify address mapping

1.5.2

Crossbar switch (XBAR)

The XBAR multiport crossbar switch supports simultaneous connections between four master ports and four slave ports. The

crossbar supports a 32-bit address bus width and a 64-bit data bus width.

The crossbar allows three concurrent transactions to occur from the master ports to any slave port but each master must access

a different slave. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher

priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher

priority master completes its transactions. Requesting masters are treated with equal priority and are granted access to a slave

port in round-robin fashion, based upon the ID of the last master to be granted access. The crossbar provides the following

features:

•

4 master ports

— CPU instruction bus

— CPU data bus

—eDMA

—FlexRay

•

4 slave ports

—Flash

— Calibration bus interface

—SRAM

— Peripheral bridge

•

32-bit internal address, 64-bit internal data paths

1.5.3

Enhanced direct memory access (eDMA)

The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data

movements via 64 programmable channels, with minimal intervention from the host processor. The hardware

micro-architecture includes a DMA engine which performs source and destination address calculations, and the actual data

movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels.

This implementation minimizes overall block size. The eDMA module provides the following features:

•

All data movement via dual-address transfers: read from source, write to destination

•

Programmable source and destination addresses, transfer size, plus support for enhanced addressing modes

•

Transfer control descriptor organized to support two-deep, nested transfer operations

•

An inner data transfer loop defined by a “minor” byte transfer count

•

An outer data transfer loop defined by a “major” iteration count

•

Channel activation via one of three methods:

— Explicit software initiation

— Initiation via a channel-to-channel linking mechanism for continuous transfers

— Peripheral-paced hardware requests (one per channel)

•

Support for fixed-priority and round-robin channel arbitration

•

Channel completion reported via optional interrupt requests

•

1 interrupt per channel, optionally asserted at completion of major iteration count

•

Error termination interrupts optionally enabled

•

Support for scatter/gather DMA processing

•

Ability to suspend channel transfers by a higher priority channel

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